參數(shù)資料
型號： TMS320DM647_08
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 66/167頁
文件大小： 1438K
代理商： TMS320DM647_08
www.ti.com
P
6.5.1
PLL2 Controller Device-Specific Information
6.5.2
PLL2 Controller Operating Modes
6.5.3
PLL2 Controller Input Clock Electrical Data/Timing
CLKIN
2
3
4
4
5
1
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372A–MAY 2007–REVISED JUNE 2007
DSP device as possible. For the best performance, TI requires that all the PLL external components be on
a single side of the board without jumpers, switches, or components other than the ones shown. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C161, C162, and the EMI Filter). The minimum CLKIN2 rise and fall times should also be observed. For
the input clock timing requirements, see
Section 6.5.3
, PLL2 Controller Input Clock Electrical Data/Timing.
As shown in
Figure 6-7
, the output of PLL2, PLLOUT, is directly fed to the DDR2 memory controller. This
clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUTz. Note that,
internally, the data bus interface of the DDR2 memory controller is clocked by SYSCLK1 of the PLL1
controller.
Note that there is a minimum and maximum operating frequency for PLLREF, and PLLOUT. The clock
generator must not be configured to exceed any of these constraints. For the PLL clocks input and output
frequency ranges, see
Table 6-10
.
Table 6-10. PLL2 Clock Frequency Ranges
REQUIRED FREQUENCY
CLOCK SIGNAL
PLLREF (CLKIN2 )
PLLOUT (DDR2 clock)
UNIT
MHz
MHz
26.6
533
Unlike the PLL1 controller that can operate in bypass and a PLL mode, the PLL2 controller only operates
in PLL mode. PLL2 isunlocked only during the power-up sequence (see
Section 6.7
) and is locked by the
time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
Table 6-11. Timing Requirements for CLKIN2
(1)(2)
(see
Figure 6-8
)
-720
-900
NO.
UNIT
PLL MODES x20
MIN
37.5
0.4C
0.4C
MAX
37.5
1
2
3
4
5
t
c(CLKIN2)
t
w(CLKIN2H)
t
w(CLKIN2L)
t
t(CLKIN2)
t
J(CLKIN2)
Cycle time, CLKIN2
Pulse duration, CLKIN2 high
Pulse duration, CLKIN2 low
Transition time, CLKIN2
Period jitter, (peak-to-peak) CLKIN2
ns
ns
ns
ns
ps
1.2
100
(1)
(2)
The reference points for the rise and fall transitions are measured at 3.3-V V
MAX and V
MIN.
C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns.
Figure 6-8. CLKIN2 Timing
66
Peripheral Information and Electrical Specifications
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