參數(shù)資料
型號: TMS320C10-25
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(160ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的DSP)
中文描述: 數(shù)字信號處理器(160ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的數(shù)字信號處理器)
文件頁數(shù): 44/139頁
文件大?。?/td> 1478K
代理商: TMS320C10-25
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
44
reset timing
tsu(RS)
tsu(RS)
tw(RS)
tdis(RS-DB)
td(RS-RW)
CLKOUT
RS
REN
WE
D15-D0
ADDRESS
BUS
(see
Note E)
Data Shown Relative To WE
Data In From
PC ADDR 0
Data In From
PC ADDR PC+1
AB = Address Bus
AB = PC
AB = PC = 0
AB = PC+1
tdis(RS-RW)
tdis(RS-AB)
ten(RS-AB)
Data Out
NOTES: A. RS forces REN, and WE high and then places data bus D0-D15, REN, WE, and address bus A0-A11 in a high-impedance state.
AB outputs (and program counter) are synchronously cleared to zero after the next complete CLK cycle from RS
.
B. RS must be maintained for a minimum of five clock cycles.
C. Resumption of normal program will commence after one complete CLK cycle from RS
.
D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS
or RS
occur in the CLK
cycle.
E. Diagram shown is for definition purpose only. WE and REN are mutually exclusive.
microcomputer/microprocessor mode timing
CLKOUT
RS
th(MC/MP)
NMI/MC/MP
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