參數(shù)資料
型號(hào)： TMS320C10-25
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號(hào)處理器（160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號(hào)處理器）
文件頁數(shù)： 121/139頁
文件大?。?/td> 1478K
代理商： TMS320C10-25
RL = 825
,
CL = 100 pF,
(see Figure 2)
RL = 825
,
CL = 100 pF,
(see Figure 2)
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
121
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
277.78
NOM
MAX
1000
UNIT
ns
tc(C)
tr(C)
tf(C)
tw(CL)
tw(CH)
td(MCC)Delay time CLKIN
↑
to CLKOUT
↓
§tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used).
Values derived from characterization data and not tested
CLKOUT cycle time§
CLKOUT rise time
10
8
ns
CLKOUT fall time
ns
Pulse duration, CLKOUT low
131
ns
Pulse duration, CLKOUT high
129
ns
25
75
ns
timing requirements over recommended operating conditions
MIN
NOM
MAX
UNIT
tc(MC)
tr(MC)
tf(MC)
tw(MCP)Pulse duration, master clock
tw(MCL)Pulse duration, master clock low at tc(MC) min
tw(MCH)Pulse duration, master clock high at tc(MC) min
Values derived from characterization data and not tested.
Master clock cycle time
69.5
150
10
10
ns
Rise time, master clock input
5
5
ns
Fall time, master clock input
ns
0.4tc(MC)
0.6tc(MC)
30
ns
ns
30
ns
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
10
1/4 tc(C)–5
–10
1/2 tc(C)–5 1/2 tc(C)+25
–10
MAX
UNIT
td1
td4
td5
td6
td7
td8
td9
td10
tv
th(A-WMD)
tsu(A-MD)
Values derived from characterization data and not tested.
NOTE 14:
Address bus will be valid upon WE
↑
, MEN
↑
, or DEN
↑
.
Delay time CLKOUT
↓
to address bus valid
Delay time CLKOUT
↓
to DEN
↓
Delay time CLKOUT
↓
to DEN
↑
Delay time CLKOUT
↓
to WE
↓
Delay time CLKOUT
↓
to WE
↑
Delay time CLKOUT
↓
to data bus OUT valid
Time after CLKOUT
↓
that data bus starts to be driven
Time after CLKOUT
↓
that data bus stops being driven
Data bus OUT valid after CLKOUT
↓
Address hold time after WE
↑
,
MEN
↑
, or
DEN
↑
(see Note 14)
100
ns
1/4 tc(C)+25
ns
30
ns
ns
30
ns
1/4 tc(C)+130
ns
1/4 tc(C)–5
ns
1/4 tc(C)+90
ns
1/4 tc(C)–10
0
ns
ns
Address bus setup time or DEN
↓
0
ns
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