參數(shù)資料
型號： TMS320C10-14
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(280ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（280ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 96/139頁
文件大?。?/td> 1478K
代理商： TMS320C10-14
TMS320C17, TMS320E17, TMS320LC17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
96
architecture
The
′
C17/E17/LC17/P17 consists of five major functional units: the
′
C15 microcomputer, a system control
register, a full-duplex dual-channel serial port, companding hardware, and a coprocessor port.
Three of the I/O ports are used by the serial port, companding hardware, and the coprocessor port. Their
operation is determined by the 32 bits of the system control register (see Table 6 for the control register bit
definitions). Port 0 accesses control register 0 and consists of the lower 16 register bits (CR15-CR0), and is used
to control the interrupts, serial port connections, and companding hardware operation. Port 1 accesses control
register 1, consisting of the upper 16 control bits (CR31-CR16), as well as both serial port channels, the
companding hardware, and the coprocessor port channels. Communication with the control register is via IN
and OUT instructions to ports 0 and 1.
Interrupts fully support the serial port interface. Four maskable interrupts (EXINT, FR, FSX, and FSR) are
mapped into I/O port 0 via control register 0. When disabled, these interrupts may be used as single-bit logic
inputs polled by software.
serial port
The dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two
combo-codecs. Two receive and two transmit registers are mapped into I/O port 1, and operate with 8-bit data
samples. Internal and external framing signals for serial port transfers (MSB first) are selected via the system
control register. The serial port clock, SCLK, provides the bit timing for transfers with the serial port, and may
be either an input or output. As an input, an external clock provides the timing for data transfers and framing
pulse synchronization. As an output, SCLK provides the timing for standalone serial communication and is
derived from the
′
C17/E17/P17 system clock, X2/CLKIN, and system control register bits CR27-CR24
(see Table 7 for the available divide ratios). The internal framing (FR) pulse frequency is derived from the serial
port clock (SCLK) and system control register bits CR23-CR16. This framing pulse signal provides framing
pulses for combo-codecs, for a sample clock for voice-band systems, or for a timer used in control applications.
μ
-law/A-law companding hardware
The
′
C17/E17/LC17/P17 features hardware companding logic and can operate in either
μ
-law or A-law format
with either sign-magnitude or twos-complement numbers. Data may be companded in either a serial mode for
operation on serial port data or a parallel mode for computation inside the device. The companding logic
operation is selected through CR14. No bias is required when operating in twos-complement. A bias of 33 is
required for sign-magnitude in
μ
-law companding. Upon reset, the device is programmed to operate in
sign-magnitude mode. This mode can be changed by modifying control bit 29 (CR29) in control register 1. For
further information on companding, see the TCM29C13/TCM29C14/TCM29C16/TCM29C17 Combined
Single-Chip PCM Codec and Filter Data Sheet and the application report, “Companding Routines for the
TMS32010/TMS32020,”in the book Digital Signal Processing Applications with the TMS320 Family
(SPRA012A), both documents published by Texas Instruments.
In the serial mode, sign-magnitude linear PCM (13 magnitude bits plus 1 sign bit for
μ
-law format or 12
magnitude bits plus 1 sign bit for A-law format) is compressed to 8-bit sign-magnitude logarithmic PCM by the
encoder and sent to the transmit register for transmission on an active framing pulse. The decoder converts 8-bit
sign-magnitude log PCM from the serial port receive registers to sign-magnitude linear PCM.
In the parallel mode, the serial port registers are disabled to allow parallel data from internal memory to be
encoded or decoded for computation inside the device. In the parallel encode mode, the encoder is enabled
and a 14-bit sign-magnitude value written to port 1. The encoded value is returned with an IN instruction from
port 1. In the parallel decode mode, the decoder is enabled and an 8-bit sign-magnitude log PCM value is written
to port 1. On the successive IN instruction from port 1, the decoded value is returned. At least one instruction
should be inserted between an OUT and the successive IN when companding is performed with
twos-complement values.
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