參數(shù)資料
型號(hào)： TMS320C10-14
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(280ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號(hào)處理器（280ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號(hào)處理器）
文件頁數(shù)： 58/139頁
文件大?。?/td> 1478K
代理商： TMS320C10-14
UNIT
RL = 825
,
CL = 100 pF
(see Figure 2)
TEST
CONDITIONS
PARAMETER
UNIT
RL = 825
,
CL = 100 pF
(see Figure 2)
UNIT
TEST
CONDITIONS
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
58
timing requirements over recommended operating conditions
TMS320C15/E15/P15
TMS320C15-25/E15-25
MIN
NOM
MAX
MIN
NOM
MAX
tc(MC)
tr(MC)
tf(MC)
tw(MCP)
tw(MCL)
tw(MCH)
Values derived from characterization data and not tested.
Master clock cycle time
48.78
50
5
5
150
10
10
39.06
40
5
5
0.55tc(MC)
15
15
150
10
10
ns
Rise time, master clock input
ns
Fall time, master clock input
ns
Pulse duration, master clock
0.4tc(MC)
0.6tc(MC)
20
20
0.45tc(MC)
ns
Pulse duration, master clock low
ns
Pulse duration, master clock high
ns
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
TMS320C15/E15/P15
TMS320C15-25/E15-25
MIN
NOM
MAX
MIN
NOM
MAX
td1
Delay time, CLKOUT
↓
to
address bus valid
10
50
10
40
ns
td2
td3
td4
td5
td6
td7
Delay time, CLKOUT
↓
to MEN
↓
Delay time, CLKOUT
↓
to MEN
↑
Delay time, CLKOUT
↓
to DEN
↓
Delay time, CLKOUT
↓
to DEN
↑
Delay time, CLKOUT
↓
to WE
↓
Delay time, CLKOUT
↓
to WE
↑
Delay time, CLKOUT
↓
to data bus
OUT valid
1/4tc(C) – 5
–10
1/4tc(C)– 5
–10
1/2tc(C)– 5
–10
1/4tc(C)+15
1/4tc(C)– 5
–10
1/4tc(C)– 5
–10
1/2tc(C)– 5
–10
1/4tc(C)+12
ns
15
12
ns
1/4tc(C)+15
1/4tc(C)+12
ns
15
12
ns
1/2tc(C)+15
1/2tc(C)+12
ns
15
12
ns
td8
1/4tc(C)+65
1/4tc(C)+52
ns
td9
Time after CLKOUT
↓
that data bus
starts to be driven
1/4tc(C)– 5
1/4tc(C)– 5
ns
td10
Time after CLKOUT
↓
that
data bus stops being driven
(TMS320C15/C15-25 only)
1/4tc(C)+ 40
1/4tc(C)+ 40
ns
td10
Time after CLKOUT
↓
that
data bus stops being driven
(TMS320E15/E15-25 only)
1/4tc(C)+ 70
1/4tc(C)+70
ns
tv
Data bus OUT valid after CLKOUT
↓
Address hold time after WE
↑
, MEN
↑
,
or DEN
↑
(see Note 15)
1/4tc(C)– 10
1/4tc(C)– 10
ns
th(A-WMD)
0
2
0
2
ns
tsu(A-MD)
Address bus setup time prior to
DEN
↓
Values derived from characterization data and not tested.
NOTE 14: Address bus will be valid upon WE
↑
, MEN
↑
, or DEN
↑
.
timing requirements over recommended operating conditions
1/4tc(C)–45
1/4tc(C)–35
ns
TMS320C15/E15/P15
TMS320C15-25/E15-25
MIN
NOM
MAX
MIN
NOM
MAX
tsu(D)
Setup time, data bus valid prior to CLKOU-
T
↓
50
40
ns
th(D)
Hold time, data bus held valid after
CLKOUT
↓
(see Note 9)
Data may be removed from the data bus upon MEN
↑
or DEN
↑
preceding CLKOUT
↓
.
0
0
ns
NOTE 9:
相關(guān)PDF資料
PDF描述
TMS320C10-25 Digital Signal Processors(160ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
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