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Table of Contents
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 CPU Core Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 Memory Address Map............................................................................................................................. 11
2.1.2 Program Memory (Flash)........................................................................................................................ 12
2.1.3 Data Memory (RAM)............................................................................................................................... 12
2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 Clock Generator...................................................................................................................................... 13
2.2.2 Timing Generator.................................................................................................................................... 14
2.2.2.1 Timing Generator Configuration
2.2.3 Operating Modes .................................................................................................................................... 16
2.2.4 Operating Mode Control ......................................................................................................................... 21
2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.1 External Reset Input ............................................................................................................................... 36
2.3.2 Address-Trap-Reset ............................................................................................................................... 37
2.3.3 Watchdog Timer Reset ........................................................................................................................... 37
2.3.4 System Clock Reset ............................................................................................................................... 37
3.1 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.1 Interrupt master enable flag (IMF) .......................................................................................................... 40
3.2.2 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 41
3.3 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4.1 Interrupt acceptance processing is packaged as follows........................................................................ 43
3.4.2 Saving/restoring general-purpose registers............................................................................................ 44
3.4.2.1 Using PUSH and POP instructions
3.4.2.2 Using data transfer instructions
3.4.3 Interrupt return ........................................................................................................................................ 46
3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.5.1 Address error detection .......................................................................................................................... 47