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參數(shù)資料
| 型號(hào)： | TMP320F28044ZGMS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processor |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 15/107頁(yè) |
| 文件大小： | 784K |
| 代理商： | TMP320F28044ZGMS |
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TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
Table 2-2. Signal Descriptions (continued)
PIN NO.
GGM/
ZGM
BALL #
NAME
DESCRIPTION
(1)
PZ
PIN #
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
be tied to GND. (I)
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2. If X2 is not used it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD,
↑
)
The output buffer of this pin is an open-drain with an internal pullup (100
μ
A, typical). It is
recommended that this pin be driven by an open-drain device.
ADC SIGNALS
ADC Group A, Channel 7 input (I)
ADC Group A, Channel 6 input (I)
ADC Group A, Channel 5 input (I)
ADC Group A, Channel 4 input (I)
ADC Group A, Channel 3 input (I)
ADC Group A, Channel 2 input (I)
ADC Group A, Channel 1 input (I)
ADC Group A, Channel 0 input (I)
ADC Group B, Channel 7 input (I)
ADC Group B, Channel 6 input (I)
ADC Group B, Channel 5 input (I)
ADC Group B, Channel 4 input (I)
ADC Group B, Channel 3 input (I)
ADC Group B, Channel 2 input (I)
ADC Group B, Channel 1 input (I)
ADC Group B, Channel 0 input (I)
Low Reference (connect to analog ground) (I)
ADC External Current Bias Resistor. Connect a 22-k
resistor to analog ground.
External reference input (I)
Internal Reference Positive Output. Requires a low ESR (50 m
- 1.5
) ceramic bypass capacitor
of 2.2
μ
F to analog ground. (O)
Internal Reference Medium Output. Requires a low ESR (50 m
- 1.5
) ceramic bypass capacitor
of 2.2
μ
F to analog ground. (O)
CPU AND I/O POWER PINS
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
ADC Analog I/O Power Pin (3.3 V)
ADC Analog I/O Ground Pin
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
X1
88
E6
X2
86
C6
XRS
78
B8
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCLO
ADCRESEXT
ADCREFIN
16
17
18
19
20
21
22
23
34
33
32
31
30
29
28
27
24
38
35
F3
F4
G4
G1
G2
G3
H1
H2
K5
H4
K4
J4
K3
H3
J3
K2
J1
F5
J5
ADCREFP
37
G5
ADCREFM
36
H5
V
DDA2
V
SSA2
V
DDAIO
V
SSAIO
V
DD1A18
V
SS1AGND
V
DD2A18
V
SS2AGND
15
14
26
25
12
13
40
39
F2
F1
J2
K1
E4
E5
J6
K6
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Introduction
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