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參數(shù)資料
| 型號： | TMP320F28044PZS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 64/107頁 |
| 文件大小： | 784K |
| 代理商： | TMP320F28044PZS |
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TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
Table 4-11. F28044 GPIO MUX Table
GPxMUX1/2
(1)
REGISTER
BITS
DEFAULT AT
RESET
PRIMARY I/O
FUNCTION
(GPxMUX1/2
BITS = 0,0)
PERIPHERAL
SELECTION 1
(2)
(GPxMUX1 BITS = 0,1)
GPAMCFG(EPWMMODE)
(3)
0,0
(4)
PERIPHERAL
SELECTION 2
(2)
(GPxMUX1/2 BITS = 1,0)
PERIPHERAL
SELECTION 3
(2)
(GPxMUX1/2 BITS =
1,1)
1,1
GPAMUX1
EPWM1A (O)
EPWM2A (O)
EPWM3A (O)
EPWM4A (O)
EPWM5A (O)
EPWM6A (O)
EPWM7A (O)
EPWM8A (O)
EPWM9A (O)
EPWM10A (O)
EPWM11A (O)
EPWM12A (O)
EPWM13A (O)
EPWM14A (O)
EPWM15A (O)
EPWM16A (O)
GPAMUX2
1-0
3-2
5-4
7-6
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
TZ1 (I)
TZ2 (I)
TZ3 (I)
TZ4 (I)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EPWMSYNCI (I)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EPWMSYNCO (O)
Reserved
ADCSOCAO (O)
Reserved
ADCSOCBO (O)
Reserved
Reserved
Reserved
Reserved
Reserved
1-0
3-2
5-4
7-6
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCIRXDA (I)
SCITXDA (O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TZ5 (I)
TZ6 (I)
TZ1 (I)
TZ2 (I)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TZ5 (I)
TZ6 (I)
TZ3 (I)
TZ4 (I)
GPBMUX1
1-0
3-2
5-4
GPIO32
GPIO33
GPIO34
SDAA (I/OC)
SCLA (I/OC
)
Reserved
EPWMSYNCI (I)
EPWMSYNCO (O)
Reserved
ADCSOCAO (O)
ADCSOCBO (O)
Reserved
(1)
(2)
GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
The options GPAMCFG(EPWMMODE) = 0, 1 and 1, 0 are reserved.
This is the default configuration upon reset.
(3)
(4)
Peripherals
64
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