參數(shù)資料
型號： TMP320C6205GHK200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 43/72頁
文件大?。?/td> 1143K
代理商： TMP320C6205GHK200
SPRS106G OCTOBER 1999 REVISED JULY 2006
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 21)
NO.
200
UNIT
MIN
MAX
7
tsu(EDV-CKO2H)
th(CKO2H-EDV)
Setup time, read EDx valid before CLKOUT2 high
1.25
ns
8
Hold time, read EDx valid after CLKOUT2 high
3
ns
switching characteristics over recommended operating conditions for synchronous DRAM
cycles
(see Figure 21Figure 26)
NO.
PARAMETER
200
UNIT
MIN
MAX
1
tosu(CEV-CKO2H)
toh(CKO2H-CEV)
tosu(BEV-CKO2H)
toh(CKO2H-BEIV)
tosu(EAV-CKO2H)
toh(CKO2H-EAIV)
tosu(CASV-CKO2H)
toh(CKO2H-CASV)
tosu(EDV-CKO2H)
toh(CKO2H-EDIV)
tosu(WEV-CKO2H)
toh(CKO2H-WEV)
tosu(SDA10V-CKO2H)
toh(CKO2H-SDA10IV)
tosu(RASV-CKO2H)
toh(CKO2H-RASV)
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
Output setup time, CEx valid before CLKOUT2 high
P 1
ns
2
Output hold time, CEx valid after CLKOUT2 high
P 3.5
ns
3
Output setup time, BEx valid before CLKOUT2 high
P 1
ns
4
Output hold time, BEx invalid after CLKOUT2 high
P 3.5
ns
5
Output setup time, EAx valid before CLKOUT2 high
P 1
ns
6
Output hold time, EAx invalid after CLKOUT2 high
P 3.5
ns
9
Output setup time, SDCAS/SSADS valid before CLKOUT2 high
P 1
ns
10
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
Output setup time, EDx valid before CLKOUT2 high§
P 3.5
ns
11
P 3
ns
12
Output hold time, EDx invalid after CLKOUT2 high
P 3.5
ns
13
Output setup time, SDWE/SSWE valid before CLKOUT2 high
P 1
ns
14
Output hold time, SDWE/SSWE valid after CLKOUT2 high
P 3.5
ns
15
Output setup time, SDA10 valid before CLKOUT2 high
P 1
ns
16
Output hold time, SDA10 invalid after CLKOUT2 high
P 3.5
ns
17
Output setup time, SDRAS/SSOE valid before CLKOUT2 high
P 1
ns
18
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
P 3.5
ns
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