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參數(shù)資料
| 型號： | TMDS442PNP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | GREEN, PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 21/45頁 |
| 文件大?。?/td> | 1977K |
| 代理商： | TMDS442PNP |
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Example - Writing to the TMDS442
SLLS757A – AUGUST 2006 – REVISED MARCH 2007
Table 3. TMDS442 Sink Port Register Bit Decoder (continued)
BIT
FUNCTION
BIT VALUES
RESULT
00
Source port 1 select
01
Source port 2 select
1, 0
SB SA
10
Source port 3 select
11
Source port 4 select
Bits 7 (MSB), 6 and 5 – Reserved bits without function.
Bit 4 – Controls the TMDS output differential voltage.
Bit 3 – Controls the status of DDC interface, SCL_SINK and
SDA_SINK.
Bit 2 – Controls the status of TMDS interface, Y/Z.
Bits 1, and 0 (LSB) – Selects the source input of the TMDS442.
The 5-V plug in status can be read through each bit of the sub-address (source plug-in status) status register.
Each bit of the third sub-address, source plug-in status registers, allows the user to read the cable plug-in status
based on the appearance of a valid +5-V power signal from each source input port. The bit description is
decoded in Table 4.
Table 4. TMDS442 Source Plug-In Status Register Bit Decoder
BIT
FUNCTION
BIT VALUES
RESULT
7, 6
Reserved
0 0
Default value
0
Sink port1 is the main display when the same source is selected by both sinks
5
SP
1
Sink port2 is the main display when the same source is selected by both sinks
0
TMDS output status is not controlled by the corresponding +5-V power signal
4
5V_EN
1
TMDS output status is controlled by the corresponding +5-V power signal
0
Source side I2C buffer is disabled (Hi-Z) When source port 4 is selected by sink,
TMDS is Hi-Z
3
5V_PWR4
1
Source side I2C buffer is enabled When source port 4 is selected by sink, TMDS is
under the control of OE
0
Source side I2C buffer is disabled (Hi-Z)
2
5V_PWR3
1
When source port 3 is selected by sink, TMDS is Hi-Z
0
Source side I2C buffer is disabled (Hi-Z) When source port 2 is selected by sink,
TMDS is Hi-Z
1
5V_PWR2
1
Source side I2C buffer is enabled When source port 2 is selected by sink, TMDS is
under the control of OE
0
Source side I2C buffer is disabled (Hi-Z) When source port 1 is selected by sink,
TMDS is Hi-Z
0
5V_PWR1
1
Source side I2C buffer is enabled When source port 1 is selected by sink, TMDS is
under the control of OE
The proper way to write to the TMDS442 is illustrated as follows:
An I2C master initiates a write operation to the TMDS442 by generating a start condition (S) followed by the
TMDS442 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TMDS442, the master presents the sub-address (sink port) it wants to write
consisting of one byte of data, MSB first. The TMDS442 acknowledges the byte after completion of the transfer.
Finally the master presents the data it wants to write to the register (sink port) and the TMDS442 acknowledges
the byte. The I2C master then terminates the write operation by generating a stop condition (P). Note that the
TMDS442 does not support multi-byte transfers. To write to both sink ports – or registers - this procedure must
be repeated for each register one series at a time (i.e. repeat steps 1 through 8 for each sink port).
28
Copyright 2006–2007, Texas Instruments Incorporated
Product Folder Link(s): TMDS442
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