參數(shù)資料
型號: TMDS3740855-02
廠商: Texas Instruments, Inc.
英文描述: TMS370 MICROCONTROLLER FAMILY DATA BOOK
中文描述: TMS370微控制器系列數(shù)據(jù)手冊
文件頁數(shù): 39/78頁
文件大小: 919K
代理商: TMDS3740855-02
GLOSSARY/SYMBOLS, TERMS, AND DEFINITIONS
1–31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
CSPF:
to external frames of the peripheral field (locations 10C0h – 10FFh).
Chip-Select Peripheral File. This signal has the same timing as EDS, but it goes active only during access
D
data:
Any information stored in or retrieved from a memory device.
debugger:
emulator, CDT370, or design kit.
A window-oriented software interface that helps the user to debug ’370 programs running on an
dedicated-capture registers:
at the time of a specified edge on one of the PACT input-capture pins. Unlike the circular buffer, the location of
the dedicated-capture register does not change.
An area in the PACT module dual-port RAM that stores the value of the default timer
default timer (also hardware timer):
PACT prescaled clock
A 20-bit hardware counter in the PACT module that is incremented by the
design kit:
family.
A low-cost tool that allows the user to analyze the hardware and software capabilities of the TMS370
DIP:
Dual In-line Package
dual-port RAM:
module.
An area in RAM that can be read from and written to by both the TMS370 CPU and the PACT
E
edge detection:
propriate output transitions to the rest of the module. The active transition can be configured to be low-to-high or
high-to-low.
A type of circuitry that senses an active pulse transition on a given timer input and provides ap-
EDS:
External Data Strobe. This signal goes low during external-memory operations. The rising edge of EDS vali-
dates the read-input data; the write data is available after the falling edge of EDS.
EEPROM:
under direct program control.
Electrically Erasable Programmable Read-Only Memory.Memory that can be programmed and erased
EPROM:
control.
Erasable Programmable Read-Only Memory.Memory that can be programmed under direct program
Erase:
and the device returns to its unprogrammed state.
Typically associated with EPROM and EEPROM. The procedure whereby programmed data is removed
ESD:
Electrostatic discharge
F
fully-static RAM:
therefore always active and ready to respond to input changes without the need of clocks. There is no precharge
required for static periphery.
In a fully-static RAM, the periphery as well as the memory array is fully static. The periphery is
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