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參數(shù)資料
| 型號： | TMDS261PAGR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 27/43頁 |
| 文件大?。?/td> | 2160K |
| 代理商： | TMDS261PAGR |
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S
Slave Address
W
A
Data
A
Data
A
P
FromReceiver
From Transmitter
A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R0007-01
Acknowledge
(FromReceiver)
Start
Condition
Acknowledge
(Receiver)
Acknowledge
(Receiver)
SDA
Stop
Condition
I CDevice Addressand
Read/WriteBit
2
FirstDataByte
Other
DataBytes
LastDataByte
A6
ACK
A5
A1
A0
R/W
D7
D6
D1
D0 ACK
D7
D6
D1
D0
ACK
T0397-01
S
Slave Address
W
A
Data
A
Data
A
P
Receiver
Transmitter
A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R=Read
R0008-01
Start
Condition
SDA
Acknowledge
(FromReceiver)
Acknowledge
(From Transmitter)
Not Acknowledge
(Transmitter)
Stop
Condition
LastDataByte
I CDevice Addressand
Read/WriteBit
2
FirstData
Byte
Other
DataBytes
A6
A0
ACK
R/W
D7
D0
ACK
D7
D6
D1
D0
ACK
T0398-01
Slave Address
www.ti.com............................................................................................................................................................................................ SLLS953 – DECEMBER 2008
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 42 and Figure 43.
Note that the TMDS261 allows multiple write transfers to occur. See the Example – Writing to the TMDS261
section for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not-acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 44 and Figure 45.
See the Example – Reading from the TMDS261 section for more information.
Figure 42. I2C Write Cycle
Figure 43. Multiple-Byte Write Transfer
Figure 44. I2C Read Cycle
Figure 45. Multiple-Byte Read Transfer
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. These resistors should
comply with the I2C specification that ranges from 2 k
to 19 k. When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The 7-bit address is
factory preset to 0101 100. Table 7 lists the calls that the TMDS261 responds to.
Copyright 2008, Texas Instruments Incorporated
33
Product Folder Link(s) :TMDS261
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