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    參數(shù)資料
    型號: TMC22191KHC
    廠商: FAIRCHILD SEMICONDUCTOR CORP
    元件分類: 顏色信號轉換
    英文描述: Digital Video Encoders/Layering Engine
    中文描述: COLOR SIGNAL ENCODER, PQFP100
    封裝: 3.20 MM HEIGHT, MQFP-100
    文件頁數(shù): 53/60頁
    文件大?。?/td> 293K
    代理商: TMC22191KHC
    PRODUCT SPECIFICATION
    TMC22091/TMC22191
    53
    Figure 37. TMC22x91-to-TMC22071 Interface Circuit
    2
    8
    8
    27009A
    CVBS7-0
    GHSYNC
    GVSYNC
    PXCK
    R
    D
    A
    C
    R
    LDV
    CVBS7-0
    GHSYNC
    GVSYNC
    PXCK
    LDV
    MICROPROCESSOR
    INTERFACE
    GENLOCKING VIDEO DIGITIZER
    TMC22071
    DIGITAL VIDEO ENCODER
    TMC22x91
    R
    D
    A
    C
    R
    Printed Circuit Board Layout
    Designing with high-performance mixed-signal circuits
    demands printed circuits with ground planes. Overall system
    performance is strongly influenced by the board layout.
    Capacitive coupling from digital to analog circuits may
    result in poor picture quality. Consider the following sugges-
    tions when doing the layout:
    Keep analog traces (COMP, V
    REF
    , R
    REF
    ) as short and as
    far from all digital signals as possible.
    The power plane for the TMC22x91 should be separate
    from that which supplies other digital circuitry. A single
    power plane should be used for all of the V
    DD
    pins. If the
    power supply for the TMC22x91 is the same for the
    system’s digital circuitry, power to the TMC22x91 should
    be filtered with ferrite beads and 0.1
    μ
    F capacitors to
    reduce noise.
    The ground plane should be solid, not cross-hatched.
    Connections to the ground plane should be very short.
    Decoupling capacitors should be applied liberally to V
    DD
    pins. For best results, use 0.1
    μ
    F capacitor in
    parallel with 47
    μ
    F capacitors. Lead lengths should be
    minimized. Ceramic chip capacitors are the best choice.
    The PXCK should be handled carefully. Jitter and noise
    on this clock or its ground reference will translate to noise
    on the video outputs. Terminate the clock line carefully to
    eliminate overshoot and ringing.
    Microprocessor I/O Operations
    Various CLUT Read/Write operations are shown in Table 17.
    Each step in the table requires a CS pulse (falling edge fol-
    lowed by a rising edge) to execute.
    For Write operations, R/W and A
    1-0
    must conform to setup
    and hold timing with respect to the falling edge of CS. D
    7-0
    must meet setup and hold timing with respect to the rising
    edge of CS. These timing relationships are illustrated in Fig-
    ure 10. When writing data into an internal register (i.e.
    CLUT Address Register) an extra CS falling edge is required
    to transfer the input data to that register. This requirement is
    usually accomplished by executing the next step in the
    sequence. If there is no planned next step in the sequence,
    executing a Control Register Read step will meet the require-
    ment and terminate the sequence.
    For Read operations, R/W and A
    1-0
    must conform to setup
    and hold timing with respect to the falling edge of CS. Read
    data on D
    7-0
    is initiated by the falling edge of CS\ and termi-
    nated by the rising edge of CS as shown in Figure 11. When
    reading Control Registers, valid data appears t
    DOM
    after the
    falling edge of CS. When reading CLUT locations, an extra
    CLUT Read step is needed to set up the CLUT Read
    sequence. This is accomplished in the table by executing an
    extra CLUT Read step just before the CLUT Read sequence
    which returns successive d, e, and f data. CLUT Read
    sequences must be terminated an extra CS falling edge. This
    requirement is usually accomplished by executing the next
    I/O step. If there is no planned next step in the sequence,
    executing a Control Register Read step will meet the require-
    ment and terminate the sequence.
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