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參數(shù)資料
| 型號(hào)： | TMC22071AKHC1 |
| 廠商： | Fairchild Semiconductor Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:66; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:18-35 RoHS Compliant: No |
| 中文描述： | 同步鎖相視頻數(shù)字化儀 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大小： | 125K |
| 代理商： | TMC22071AKHC1 |
TMC22071A
PRODUCT SPECIFICATION
18
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Wire-wrap is
not an option. Overall system performance is strongly influ-
enced by the board layout. Capacitive coupling from digital
to analog circuits may result in poor picture quality. Con-
sider the following suggestions when doing the layout:
1.
Keep the critical analog traces (COMP,V
REF
, R
T
, R
B
,
DDS OUT, PFD IN, C
BYP
, and V
IN1-3
) as short as pos-
sible and as far as possible from all digital signals. The
TMC22071A should be located near the board edge,
close to the analog output connectors.
2.
The digital power plane for the TMC22071A should be
that which supplies the rest of the digital circuitry. A sin-
gle power plane should be used for all of the V
DD
pins.
If the analog power supply for the TMC22071A is the
same as that of the system’s digital circuitry, power to
the TMC22071A V
DDA
pins should be decoupled with
ferrite beads and 0.1
m
F capacitors to reduce noise.
3.
The ground plane should be solid, nor cross-hatched.
Connections to the ground plane should have very short
leads.
4.
Decoupling capacitors should be applied liberally to
V
DD
pins. Remember that not all power supply pins are
created equal. They typically supply adjacent circuits on
the device, which generate varying amounts of noise.
For best results, use 0.1
m
F capacitors in parallel with
10
m
F capacitors. Lead lengths should be minimized.
Ceramic chip capacitors are the best choice.
5.
If the digital power supply has a dedicated power plane
layer, it should not overlap the TMC22071A, the voltage
reference or the analog outputs. Capacitive coupling of
digital power supply noise from this layer to the
TMC22071A and its related analog circuitry can
degrade performance.
6.
CLK should be handled carefully. Jitter and noise on
this clock or its ground reference may degrade perfor-
mance. Terminate the clock line carefully to eliminate
overshoot and ringing.
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