參數(shù)資料
型號： TLV5613DW
廠商： Texas Instruments, Inc.
英文描述： 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
中文描述： 2.7 V至5.5 V 12位并行數(shù)字至模擬轉(zhuǎn)換器與電源向下
文件頁數(shù)： 12/21頁
文件大小： 291K
代理商： TLV5613DW
TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174A – DECEMBER 1997 – REVISED JULY 1998
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
It is also possible to program the different modes (fast, slow, power down) and the DAC update latch using the
control register. The following tables list the possible combination of the control signals and control bits.
PIN
SPD
0
BIT
SPD
0
MODE
Slow
0
1
Fast
1
0
Fast
1
1
Fast
PIN
BIT
POWER
PWD
0
PWD
0
Down
0
1
Down
1
0
Normal
1
1
Down
PIN
BIT
LATCH
LDAC
0
RLDAC
0
Transparent
0
1
Transparent
1
0
Hold
1
1
Transparent
data format
The TLV5613 writes data either to one of the DAC holding latches or to the control register depending on the
address bits A1 and A0.
ADDRESS BITS
A1
A0
REGISTER
0
0
DAC LSW holding
0
1
DAC MSW holding
1
0
Reserved
1
1
Control
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
RLDAC
PWD
SPD
X: Don’t care
SPD: Speed control bit
PWD: Power control bit
RLDAC: Load DAC latch
1
→
fast mode
1
→
power down
1
→
latch transparent
0
→
slow mode
0
→
normal operation
0
→
DAC latch controlled by LDAC pin
相關PDF資料
PDF描述
TLV5613PW 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
TLV5614D 2.7-V TO 5.5-V 12-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5614PW 2.7-V TO 5.5-V 12-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5616C 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5616I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
相關代理商/技術參數(shù)
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