參數(shù)資料
型號: TLV5613DW
廠商: Texas Instruments, Inc.
英文描述: 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
中文描述: 2.7 V至5.5 V 12位并行數(shù)字至模擬轉(zhuǎn)換器與電源向下
文件頁數(shù): 11/21頁
文件大?。?/td> 291K
代理商: TLV5613DW
TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174A – DECEMBER 1997 – REVISED JULY 1998
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
POWER DOWN SUPPLY CURRENT
vs
TIME
0.00001
0.000001
100
300
t – Time – ms
0.01
0.001
0.0001
200
400
500
0
0.1
1
600
I
Figure 14
APPLICATION INFORMATION
general function
The TLV5613 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel
interface, speed and power down control logic, a resistor string and a rail-to-rail output buffer. The output voltage
(full scale determined by reference) is given by:
2 REF0x1000[V]
Where REF is the reference voltage and CODE is the digital input value, range 0x000 to 0xFFF. A power on
reset initially puts the internal latches to a defined state (all bits zero).
parallel interface
The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written
to one of the DAC holding latches (MSW, LSW) or the control register, depends on the address bits A1 and A0.
LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held
low, if a separate update is not necessary. Two more asynchronous inputs, SPD and PWD control the settling
times and the power down mode:
SPD:
PWD:
Speed control
Power control
1
fast mode
1
normal operation
0
slow mode
0
power down
相關(guān)PDF資料
PDF描述
TLV5613PW 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
TLV5614D 2.7-V TO 5.5-V 12-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5614PW 2.7-V TO 5.5-V 12-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5616C 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
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