參數(shù)資料
型號(hào): TLV5580CDWG4
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: GREEN, PLASTIC, SOIC-28
文件頁(yè)數(shù): 35/36頁(yè)
文件大?。?/td> 478K
代理商: TLV5580CDWG4
TLV5580
8BIT, 80 MSPS LOW POWER A/D CONVERTER
SLAS205B DECEMBER 1998 REVISED OCTOBER 2003
www.ti.com
8
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS WITH FCLK = 80
MSPS AND USE OF EXTERNAL VOLTAGE REFERENCES (unless otherwise noted) (continued)
DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fin = 1 MHz
6.2
6.7
Effective number of bits, ENOB
fin = 4.43 MHz
6.2
6.7
Bits
Effective number of bits, ENOB
fin = 15 MHz
6.4
Bits
fin = 76 MHz
6.5
fin = 1 MHz
39
42
Signal-to-total harmonic distortion + noise, S/(THD+N)
fin = 4.43 MHz
39
42
dB
Signal-to-total harmonic distortion + noise, S/(THD+N)
fin = 15 MHz
40
dB
fin = 76 MHz
40
fin = 1 MHz
46
50
Total harmonic distortion (THD)
fin = 4.43 MHz
45.5
49
dB
Total harmonic distortion (THD)
fin = 15 MHz
44
dB
fin = 76 MHz
45.5
fin = 1 MHz
48
51
Spurious free dynamic range (SFDR)
fin = 4.43 MHz
48
51
dB
Spurious free dynamic range (SFDR)
fin = 15 MHz
46
dB
fin = 76 MHz
48
Analog input full-power bandwidth, BW
See Note 4
700
MHz
Differential phase, DP
fclk = 40 MHz, fin = 4.43 MHz,
0.8
°
Differential phase, DP
fclk = 40 MHz, fin = 4.43 MHz,
20 IRE amplitude vs. full-scale of 140 IRE
0.8
°
Differential gain, DG
fclk = 40 MHz, fin = 4.43 MHz,
20 IRE amplitude vs. full-scale of 140 IRE
0.6
%
Differential gain, DG
20 IRE amplitude vs. full-scale of 140 IRE
0.6
%
Based on analog input voltage of 1 dBFS referenced to a 1.3 Vpp full-scale input range and using the external voltage references at
fclk = 80 MSPS with AVDD = DVDD = 3.3 V and DRVDD = 3.0 V at 25°C.
4. The analog input bandwidth is defined as the maximum frequency of a 1 dBFS input sine that can be applied to the device for which an extra
3 dB attenuation is observed in the reconstructed output signal.
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