參數(shù)資料
型號(hào)： TLV320AIC23IGQER
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： Stereo Audio CODEC, 8-to 96-kHz, With Integrated Headphone Amplifier
中文描述： 立體聲音頻編解碼器，8到96千赫，具有集成耳機(jī)放大器
文件頁(yè)數(shù)： 27/44頁(yè)
文件大?。?/td> 236K
代理商： TLV320AIC23IGQER
3
–
7
3.2.5
Analog Bypass Mode
The TLV320AIC23 includes a bypass mode in which the analog line inputs are directly routed to the analog line
outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the analog audio path control
register[see Section 3.1.3).
For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and headphone
output volume controls and mutes are still operational in bypass mode. Therefore the line inputs, DAC output, and
microphone input can be summed together. The maximum signal at any point in the bypass path must be no greater
than 1.0V
rms
at AV
DD
=3.3V to avoid clipping and distortion. This amplitude tracks linearly with AV
DD
.
3.2.6
Sidetone Insertion
The TLV320AIC23 has a sidetone insertion made where the microphone input is routed to the line and headphone
outputs. This is useful for telephony and headset applications. The attenuation of the sidetone signal may be set to
–
6 dB,
–
9 dB,
–
12 dB, or
–
15 dB, by software selection (see Section 3.1.3). If this mode is used to sum the microphone
input with the DAC output and line inputs, care must be taken not to exceed signal level to avoid clipping and distortion.
3.3
Digital Audio Interface
3.3.1
Digital Audio-Interface Modes
The TLV320AIC23 supports four audio-interface modes.
Right justified
Left justified
I
2
S mode
DSP mode
The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified
mode, which does not support 32 bits).
The digital audio interface consists of clock signal BCLK, data signals DIN and DOUT, and synchronization signals
LRCIN and LRCOUT. BCLK is an output in master mode and an input in slave mode.
3.3.1.1 Right-Justified Mode
In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN or LRCOUT
(see Figure 3-5).
LRCIN/
LRCOUT
BCLK
DIN/
DOUT
n
n
–
1
0
1
n
–
1
n
1/fs
Left Channel
Right Channel
1
0
0
MSB
LSB
Figure 3
–
5. Right-Justified Mode Timing
3.3.1.2 Left-Justified Mode
In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN or LRCOUT
(see Figure 3-6)
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