![](http://datasheet.mmic.net.cn/370000/TLV320AIC11C_datasheet_16742128/TLV320AIC11C_5.png)
v
5
6
Appendix A—Register Set
Parameter Measurement Information
Mechanical Information
5–1
6–1
A–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations
Title
Figure
2–1 Timing Sequence of ADC Channel (Primary Communication Only)
2–2 Timing Sequence of ADC Channel (Primary and
Secondary Communication)
2–3 Timing Sequence of DAC Channel (Primary Communication Only)
2–4 Timing Sequence of DAC Channel (Primary and Secondary
Communication)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Typical Microphone Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Cascading
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Event Monitor Mode Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Internal Power-Down Logic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 Timing Diagram for the FS Pulse Mode (M1M0 = 00)
2–10 Timing Diagram for the SPI_CP0 Mode (M1M0 = 01)
2–11 Timing Diagram for the SPI_CP1 Mode (M1M0 = 10)
2–12 Timing Diagram for the FS Frame Mode (M1M0 = 11)
2–13 Master Device Frame-Sync Signal With Primary and Secondary
Communication ( No Slaves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–14 Master Device’s FS Output to DSP and FSD Output to the Slave
2–15 Cascade Mode Connection (to DSP Interface)
2–16 Master-Slave Frame-Sync Timing
2–17 INP and INM Internal Self-Biased Circuit (2.5 V for 5-V Operation
and 1.5 V for 3-V Operation)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–18 Differential Output Drive (Ground-Referenced)
2–19 Single-Ended Input
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–20 Single-Ended Output
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Primary Serial Communication Timing
3–2 Hardware and Software Secondary Communication Request
3–3 Device 3/Register 1 Read Operation Timing Diagram
3–4 Device 3/Register 1 Write Operation Timing Diagram
3–5 FS Output When Hardware Secondary Serial Communication
Is Requested Only Once (No Slave)
3–6 Output When Hardware Secondary Serial Communication Is
Requested (Three Slaves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–7 FS Output During Software Secondary Serial Communication Request
(No Slave)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
2–1
. . . . . .
2–2
2–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
2–3
2–4
2–6
2–6
2–7
2–9
2–9
2–10
2–10
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
2–11
2–11
2–12
2–12
. . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–13
2–13
2–14
2–14
3–1
3–2
3–3
3–4
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . .
3–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5
3–5