參數(shù)資料
型號(hào): TLV320AIC11I
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: General-Purpose Low-Voltage 1.1V to 3.6V/0 16-bit 22-KSPS DSP CODEC
中文描述: 通用低電壓1.1V至3.6V的/ 0 16位22 kSPS的DSP的解碼器
文件頁(yè)數(shù): 31/55頁(yè)
文件大小: 263K
代理商: TLV320AIC11I
3–3
3.2.1
Register Programming
All register programming occurs during secondary communication through DIN or ALTI, and data are latched and
valid on the falling edge of the SCLK during the frame-sync signal. If the default value of a particular register is desired,
that register does not need to be addressed during the secondary communication interval. The no-op command
(DS15-DS8 all set to 0) addresses the pseudo-register (register 0), and no register programming takes place during
the communication.
In addition, each register can be read back through DOUT during secondary communications by setting the read bit
(D12) to 1. When a register is in the read mode, no data can be written to the register during this cycle
.
A subsequent
secondary communication is required to return this register to the write mode.
For example, if the contents of control register 1 of device 3 are desired to be read out from DOUT, the following
procedure must be performed through DIN:
Request secondary communication by setting either D0 = 1(software request), or FC = high (hardware
request) during the primary communication interval.
During the secondary communication interval (FS), send data in through DIN using the following format:
Device Address
RW
Register Address
X
Register Content
0
1
1
1
0
0
1
x
x
x
x
x
x
x
x
x
DS15
DS0
Then, during the same frame, the following data will be read from DOUT; the last 8 bits of DOUT will contain
register 1 data.
Device Address
RW
Register Address
X
Register Content
0
1
1
x
x
x
x
x
d
d
d
d
d
d
d
d
DS15
DS0
Figure 3–3 is the timing diagram of this procedure.
DOUT
P
S
DIN
Register 1 Read
FS
Low 8 Bit (D0 – D7) is
the content of register 1
Figure 3–3. Device 3/Register 1 Read Operation Timing Diagram
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