參數(shù)資料
型號(hào)： TLV2344Y
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 運(yùn)算放大器
英文描述： QUAD OP-AMP, 10000 uV OFFSET-MAX, 1.7 MHz BAND WIDTH, UUC14
封裝： DIE-14
文件頁(yè)數(shù)： 19/42頁(yè)
文件大?。?/td> 995K
代理商： TLV2344Y
TLV2342, TLV2342Y, TLV2344, TLV2344Y
LinCMOS
LOW-VOLTAGE HIGH-SPEED
OPERATIONAL AMPLIFIERS
SLOS194 – FEBRUARY 1997
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
single-supply operation (continued)
The TLE2426 supplies an accurate voltage equal to VDD/2 while consuming very little power and is suitable for
supply voltages of greater than 4 V.
The TLV234x works well in conjunction with digital logic; however, when powering both linear devices and digital
logic from the same power supply, the following precautions are recommended:
Power the linear devices from separate bypassed supply lines (see Figure 41); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, RC decoupling may be necessary in high-frequency
applications.
–
+
Logic
Power
Supply
–
+
Logic
Power
Supply
(a) COMMON-SUPPLY RAILS
(b) SEPARATE-BYPASSED SUPPLY RAILS (preferred)
Figure 41. Common Versus Separate Supply Rails
input characteristics
The TLV234x is specified with a minimum and a maximum input voltage that, if exceeded at either input, could
cause the device to malfunction. Exceeding this specified range is a common problem, especially in
single-supply operation. The lower range limit includes the negative rail, while the upper range limit is specified
at VDD – 1 V at TA = 25°C and at VDD – 1.2 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLV234x very good input
offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS
devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant
implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the
polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset
voltage drift with time has been calculated to be typically 0.1
V/month, including the first month of operation.
Because of the extremely high input impedance and resulting low bias-current requirements, the TLV234x is
well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can
easily exceed bias-current requirements and cause a degradation in device performance.
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