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參數(shù)資料
| 型號： | TLV2221Y |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Advanced LinCMOSE RAIL-TO-RAIL VERY LOW-POWER SINGLE OPERATIONAL AMPLIFIERS |
| 中文描述： | 高級LinCMOSE軌至軌極低功耗的單運算放大器 |
| 文件頁數(shù)： | 26/29頁 |
| 文件大小： | 593K |
| 代理商： | TLV2221Y |
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TLV2221, TLV2221Y
Advanced LinCMOS
RAIL-TO-RAIL
VERY LOW-POWER SINGLE OPERATIONAL AMPLIFIERS
SLOS157A – JUNE 1996 – REVISED JANUARY 1997
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving large capacitive loads
The TLV2221 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 49
through Figure 54 illustrate its ability to drive loads greater than 100 pF while maintaining good gain and phase
margins (R
null
= 0).
A small series resistor (R
null
) at the output of the device (Figure 55) improves the gain and phase margins when
driving large capacitive loads. Figure 49 through Figure 52 show the effects of adding series resistances of
100
, 200
, 500
, and 1 k
. The addition of this series resistor has two effects: the first effect is that it adds
a zero to the transfer function and the second effect is that it reduces the frequency of the pole associated with
the output load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the approximate improvement in phase margin, equation (1) can be used.
φ
m1
tan
–1
2
×
π
×
UGB
W
×
Rnull
×
CL
φ
m1
UGBW
R
null
improvement in phase margin
unity-gain bandwidth frequency
output series resistance
load capacitance
C
L
(1)
where :
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (Figure 53 and Figure
54). To use equation (1), UGBW must be approximated from Figure 53 and Figure 54.
VDD–/GND
VDD+
Rnull
CL
VI
+
–
RL
Figure 55. Series-Resistance Circuit
The TLV2221 is designed to provide better sinking and sourcing output currents than earlier CMOS rail-to-rail
output devices. This device is specified to sink 500
μ
A and source 1 mA at V
DD
= 5 V at a maximum quiescent
I
DD
of 200
μ
A. This provides a greater than 80% power efficiency.
When driving heavy dc loads, such as 2 k
, the positive edge under slewing conditions can experience some
distortion. This condition can be seen in Figure 37. This condition is affected by three factors:
Where the load is referenced. When the load is referenced to either rail, this condition does not occur. The
distortion occurs only when the output signal swings through the point where the load is referenced.
Figure 38 illustrates two 2-k
load conditions. The first load condition shows the distortion seen for a 2-k
load tied to 2.5 V. The third load condition in Figure 38 shows no distortion for a 2-k
load tied to 0 V.
Load resistance. As the load resistance increases, the distortion seen on the output decreases. Figure 38
illustrates the difference seen on the output for a 2-k
load and a 100-k
load with both tied to 2.5 V.
Input signal edge rate. Faster input edge rates for a step input result in more distortion than with slower input
edge rates.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLV2231 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Advanced LinCMOSE RAIL-TO-RAIL LOW-POWER SINGLE OPERATIONAL AMPLIFIERS |
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| TLV2231CDBV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Advanced LinCMOSE RAIL-TO-RAIL LOW-POWER SINGLE OPERATIONAL AMPLIFIERS |
| TLV2231CDBVR | 功能描述:運算放大器 - 運放 Low Power R/R RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| TLV2231CDBVRG4 | 功能描述:運算放大器 - 運放 Single LinCMOS Rail-To-Rail uPower RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風格:SMD/SMT 封裝 / 箱體:QFN-16 轉換速度:0.89 V/us 關閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
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