- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385930 > TLC876MDW (Texas Instruments, Inc.) 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS PDF資料下載
參數(shù)資料
| 型號： | TLC876MDW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | 10位20 MSPS的并行輸出CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 314K |
| 代理商： | TLC876MDW |
TLC876M TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140D – JULY 1997 – REVISED MAY 2000
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
driving the analog input (continued)
The expanded input circuit shown in Figure 15 aids in understanding the voltage offset generation when using
the external input circuit in Figure 14.
The ac coupling capacitors, C1 and C2, integrate the switching transients present at the input of the TLC876
causing a net dc bias current, I
B
, to flow into the input. The magnitude of this bias current increases with
increasing the dc signal level, V
B
, and also increases with sample frequency. When the sample clock frequency
is 20 MHz, the dc bias current is approximately 30
μ
A
at V
BIAS
equal to 3 V dc. This bias current causes an
offset error of (R1 + R2) x I
B
at the AIN terminal. Making R2 negligibly small or modifying V
BIAS
to account for
the resultant offset can compensate for this error. Note however that R2 loads the signal driving source, and
the value must be sufficient for the application.
For example, as shown in Figure 15, when V
BIAS
is 3 V and the resistor values stated above, the bias current
causes a 31.5 mV
offset from the 3 V bias, V
BIAS
, at the AIN terminal. For the TLC876, V
BIAS
can be as low
as 1 V for a 2 V peak-to-peak input signal swing.
AIN
VIN
R2
+
–
VBIAS
C1
C2
IB
R1
TLC876
CE
RSW
VB
Figure 15. Bias Current and Offset
For systems that require dc-coupling, an op-amp can level-shift a ground-referenced signal to comply with the
input requirements of the TLC876. Figure 16 shows an amplifier in an inverting mode with ac signal gain of –1.
The dc voltage at the noninverting input of the op-amp controls the amount of dc level shifting. A resistive voltage
divider attenuates the REFBF signal and the op-amp then multiplies the attenuated signal by 2. In the case
where REFBF = 1.6 V, the dc output level is 2.6 V which is approximately equal to (V(REFTF) – V(REFBF)/2.
IB(AVG) = CE (VB) fCLK
≈
30
μ
A, with RSW = 50
, CE = 5 pF, R1 = 50
, and R2 = 1 k
VOFFSET = IB
(
AVG
)
(R1 + R2)
相關PDF資料 |
PDF描述 |
|---|---|
| TLE2021(中文) | Precision, High-Speed, Low-Power Operational Amplifiers(單路，高速，精密型，低功耗，單電源運放) |
| TLE2022(中文) | Dual,Precision, High-Speed, Low-Power Operational Amplifiers(雙路精密型，低功耗，單電源運放) |
| TLE2024(中文) | Quad,Precision, High-Speed, Low-Power Operational Amplifiers(四路精密型，低功耗，單電源運放) |
| TLE2027(中文) | Low-Noise High-Speed Precision Operational Amplifiers(增強型低噪聲高速精密運放) |
| TLE2037(中文) | Low-Noise High-Speed Precision Operational Amplifiers(增強型低噪聲高速精密去補償運放) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC-8C-0750 | 制造商:KATO/COILTHREAD 功能描述: |
| TLC976C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR |
| TLC976CDGG | 功能描述:IC 10-BIT CCD SIG PROC 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| TLC976CDGGR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR |
| TLC-9C-1125 | 制造商:KATO/COILTHREAD 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。