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參數(shù)資料
| 型號(hào)： | TLC34075A-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(110MHz,視頻接口調(diào)色器) |
| 中文描述： | 顏色調(diào)色板（110MHz的，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 32/53頁 |
| 文件大?。?/td> | 394K |
| 代理商： | TLC34075A-110 |
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2-19
2.12.1
Frame Buffer Data Flow Test
The TLC34075A provides a means to check all the data entering the DAC (but before the output multiplexer
8/6 shift). When accessing these color channels, the data entering the DACs should be kept constant for
the entire MPU read cycle. This can be done either by slowing down the dot clock or ensuring that the data
is constant for a sufficiently long series of pixels. The value read is the one stored in the color palette RAM
location pointed to by the input multiplexer. The read operation causes a post-increment to point to the next
color channel, and the post-increment of blue wraps back to red as shown in the preceeding state diagram.
For example, if D<2:0> is written as 001, then three succsessive reads are performed, the values read out
are green, blue, and red in that sequence.
2.12.2
Identification Code
The ID code can be used for identification of different software versions. The ID code in the TLC34075A is
static and may be read without consideration of the dot clock or video signals. To be user-friendly, the read
postincrement also applies to the ID register, but once it falls into the color channel, it will not come back
pointing to the ID unless the value 011 is written to D<2:0> again. So, if the test register is written as 011
in D<2:0>, then six successive reads are performed, the first value read is the ID and the last value read
is green. The ID value defined here is 75h.
2.12.3
Ones Accumulation Screen Integrity Test
A technique called ones accumulation can be used to detect errors in fixed (not animated) screen displays.
This type of error detection is useful for system checkout and field diagnostics.
Each of the 256 24-bit words in the TLC34075A internal color palette RAM is composed of three bytes, one
each for the red, green, and blue components of the word. When D<2:0> are programmed with the
appropriate binary value (see Table 2–9), the TLC34075A monitors the corresponding color byte that is
output by the color palette RAM. For example, if D<2:0> are programmed with the value 100, the
TLC34075A monitors the red byte. As the current frame is scanned, for each color palette RAM word
accessed, the designated color byte is checked to see how many “1” bits it contains, and this number is
added to a temporary accumulator (the entire byte is checked, even if 6-bit mode is selected). For example,
if the designated color byte contains the value 41h (0100 0001), then the value 2 is added to the temporary
accumulator, as 41h contains two “1” bits. This process is continued until an entire frame has been scanned;
the same color byte is monitored for the entire frame. The temporary accumulator truncates any overflow
above the value 255. Due to circuit speed limitations, the ones accumulation is calculated at a speed of
(DOTCLK frequency)/2. During the vertical retrace activated by a falling edge on the TLC34075A VSYNC
input, the value in the temporary accumulator is transferred into the ones accumulation register, and then
the temporary accumulator is reset to zero (NOTE: the ones accumulation register is updated only on the
falling edge of VSYNC, not by any vertical sync pulses coded into the composite video signal). Before the
next frame scan begins, the TLC34075A automatically changes the value in D<2:0> so that the ones
accumulation performed during the next frame scan is for a different color byte (see the screen integrity test
state diagram of Figure 2–11). As long as the screen display remains fixed, the ones accumulation value
for a particular color byte should not change; if it does, an error has occurred.
2.12.4
Analog Test
Analog test is used to compare the voltage amplitudes of the analog RGB outputs to each other and to a
145-mV reference. This enables the MPU to determine whether the CRT monitor is connected to the analog
RGB outputs or not and whether the DACs are functional. To perform an analog test, D<2:0> must be set
to 111; D<7:4> are set as shown in Table 2–11. D<3> contains the result of the analog test.
The result of the analog comparison is strobed into D3 at the falling edge of an internal signal derived from
the input BLANK signal. In order to have stable inputs to the comparator, the DAC should be set to a constant
level between syncs. For normal operation, data flow check, and screen integrity test, D<7:4> must be set
to zero.
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