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參數(shù)資料
| 型號： | TLC34075A-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(110MHz,視頻接口調(diào)色器) |
| 中文描述： | 顏色調(diào)色板（110MHz的，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 24/53頁 |
| 文件大?。?/td> | 394K |
| 代理商： | TLC34075A-110 |
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2-11
2.4.5
As an example of how to use Table 2–6, suppose that the design goals specify a system with eight data bits
per pixel and the lowest possible SCLK rate. Table 2–6 shows that, for non-VGA-pass-through operation,
only mode 4 supports an eight-bit pixel depth. The lowest-possible SCLK rate within mode 4 is 1:4. This set
of conditions is selected by writing the value 1Eh to the mux control register. The pixel latching sequence
column shows that, in this mode, P<7:0> should be connected to the earliest-displayed pixel plane, followed
by P<15:8>, P<23:16>, and then P<31:24> as the last displayed pixel plane. Assuming that VCLK is
programmed as DOTCLK/4, Table 2–5 shows that the 1:4 SCLK ratio is selected by writing the value 12h
to the output clock selection register. The special nibble mode should also be disabled (see Sections 2.9.2
and 2.11.2).
Multiplex Control Register (Continued)
When the multiplex control register is loaded with 2Dh, the TLC34075A enters the VGA pass-through mode
(the same condition as the default power-up mode). Please refer to Section 2.5.4 for more details.
2.4.6
The read mask register is used to enable or disable a pixel address bit from addressing the color palette
RAM. Each palette address bit is logically ANDed with the corresponding bit from the read mask register
before addressing the palette. This function is performed after the addition of the page register bits and,
therefore, a zeroing of the read mask results in one unique palette location (location 0) and is not affected
by the palette page register contents.
Read Masking
2.5
There are 3 ways to reset the TLC34075A:
Reset
1.
2.
3.
Power-on reset
Hardware reset
Software reset
The default reset condition is VGA mode, and the values for each register are shown in Section 2.5.4. Note
also that, when the TLC34075A is reset, the SCLK and VCLK counters are reset. See Section 2.3.
2.5.1
The TLC34075A contains a power-on reset circuit. Once the voltage levels have stabilized following
power-on reset, the device is in the VGA pass-through mode.
Power-On Reset
2.5.2
The TLC34075A resets whenever RS<3:0> = HHHH and a rising edge occurs on the WR input. The more
rising WR edges occur, the more reliable the TLC34075A is reset. This scheme (bursting WR strobes until
the power supply voltage stablizes) is suggested at power-up if a hardware reset approach is used.
Hardware Reset
2.5.3
Whenever the mux control register is set for VGA pass-through mode after power-up, all registers are
initialized accordingly. Since VGA pass-through mode is the default condition at power-up and hardware
reset, the act of selecting the VGA pass-through mode through programming the mux control register is
viewed as a software reset. Therefore, whenever mux control register bits <5:0> are set to 2Dh, the
TLC34075A initiates a software reset.
Software Reset
2.5.4
The value contained in each register after hardware or software reset is shown below:
VGA Pass-Through Mode Default Conditions
Mux control register:
Input clock selection register:
Output clock selection register:
Palette page register:
2Dh
00h
3Fh
00h
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| TLC34077 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
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