參數(shù)資料
型號: TLC1551IFK
廠商: Texas Instruments, Inc.
英文描述: 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS
中文描述: 10位模擬數(shù)字轉(zhuǎn)換器與并行輸出
文件頁數(shù): 3/9頁
文件大小: 139K
代理商: TLC1551IFK
TLC1550I, TLC1550M TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
2–3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
DESCRIPTION
NAME
ANLG GND
NO.
4
NO.
3
Analog ground. The reference point for the voltage applied on terminals ANLG VDD, AIN, REF+, and REF–.
Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output.
AIN
5
4
ANLG VDD
CLKIN
6
5
Analog positive power supply voltage. The voltage applied to this terminal is designated VDD3.
Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes a
few microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied high
or left unconnected.
26
22
CS
25
21
Chip-select. CS must be low for RD or WR to be recognized by the A/D converter.
D0
13
11
Data bus output. D0 is bit 1 (LSB).
D1
14
12
Data bus output. D1 is bit 2.
D2
16
13
Data bus output. D2 is bit 3.
D3
17
14
Data bus output. D3 is bit 4.
D4
18
15
Data bus output. D4 is bit 5.
D5
19
16
Data bus output. D5 is bit 6.
D6
20
17
Data bus output. D6 is bit 7.
D7
21
18
Data bus output. D7 is bit 8.
D8
23
19
Data bus output. D8 is bit 9.
D9
24
20
Data bus output. D9 is bit 10 (MSB).
DGTL GND1
7
6
Digital ground 1. The ground for power supply DGTL VDD1 and is the substrate connection.
Digital ground 2. The ground for power supply DGTL VDD2.
Digital positive power-supply voltage 1. DGTL VDD1 supplies the logic. The voltage applied to DGTL VDD1 is
designated VDD1.
Digital positive power-supply voltage 2. DGTL VDD2 supplies only the higher-current output buffers. The voltage
applied to DGTL VDD2 is designated VDD2.
End-of-conversion. EOC goes low indicating that conversion is complete and the results have been transferred
to the output latch. EOC can be connected to the
μ
P- or DSP-interrupt terminal or can be continuously polled.
DGTL GND2
9
7
DGTL VDD1
10
8
DGTL VDD2
11
9
EOC
12
10
RD
28
24
Read input. When CS is low and RD is taken low, the data is placed on the data bus from the output latch. The
output latch stores the conversion results at the most recent negative edge of EOC. The falling edge of RD
resets EOC to a high within the td(EOC) specifications.
Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ converts
to 1111111111. Analog input voltages between REF+ and REF– convert to the appropriate result in a ratiometric
manner.
REF+
2
1
REF–
3
2
Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF– converts
to 0000000000.
WR
27
23
Write input. When CS is low, conversion is started on the rising edge of WR. On this rising edge, the ADC holds
the analog input until conversion is completed. Before and after the conversion period, which is given by tconv,
the ADC remains in the sampling mode.
Terminal numbers for FK and FN packages.
Terminal numbers for J and NW packages.
相關(guān)PDF資料
PDF描述
TLC1550IJ 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS
TLC1550I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS
TLC1550M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS
TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS
TLC1551IJ 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS
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