參數(shù)資料
型號(hào): TL16C554AI
廠商: Texas Instruments, Inc.
英文描述: ASYNCHRONOUS-COMMUNICATIONS ELEMENT
中文描述: 異步通信元
文件頁(yè)數(shù): 9/40頁(yè)
文件大?。?/td> 605K
代理商: TL16C554AI
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A
AUGUST 2001
REVISED JULY 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN
MAX
UNIT
tw4
tsu1
tsu2
th1
th2
td1
td2
NOTES:
Pulse duration, IOR low
75
ns
Setup time, CSx valid before IOR low (see Note 2)
10
ns
Setup time, A2
A0 valid before IOR low (see Note 2)
15
ns
Hold time, A2
A0 valid after IOR high (see Note 2)
0
ns
Hold time, CSx valid after IOR high (see Note 2)
0
ns
Delay time, tsu2 + tw4 + td2 (see Note 3)
Delay time, IOR high to IOR or IOW low
140
ns
50
ns
2. The internal address strobe is always active.
3. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt-identification register
and line-status register).
write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
MIN
MAX
UNIT
tw5
tsu3
tsu4
tsu5
th3
th4
th5
td3
td4
NOTE 2: The internal address strobe is always active.
Pulse duration, IOW
Setup time, CSx valid before IOW
(see Note 2)
Setup time, A2
A0 valid before IOW
(see Note 2)
Setup time, D7
D0 valid before IOW
Hold time, A2
A0 valid after IOW
(see Note 2)
Hold time, CSx valid after IOW
(see Note 2)
Hold time, D7
D0 valid after IOW
Delay time, tsu4 + tw5 + td4
Delay time, IOW
to IOW or IOR
50
ns
10
ns
15
ns
10
ns
5
ns
5
ns
25
ns
120
ns
55
ns
read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage, C
L
= 100 pF (see Note 4 and Figure 4)
PARAMETER
MIN
MAX
UNIT
ten
tdis
NOTE 4: VOL and VOH (and the external loading) determine the charge and discharge time.
Enable time, IOR
to D7
D0 valid
Disable time, IOR
to D7
D0 released
30
ns
0
20
ns
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