參數(shù)資料
型號： TL16C554AI
廠商： Texas Instruments, Inc.
英文描述： ASYNCHRONOUS-COMMUNICATIONS ELEMENT
中文描述： 異步通信元
文件頁數(shù)： 10/40頁
文件大?。?/td> 605K
代理商： TL16C554AI
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A
–
AUGUST 2001
–
REVISED JULY 2003
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td5
Delay time, INTx
↓
to TXx
↓
at start
See Note 7
8
24
RCLK
cycles
td6
Delay time, TXx
↓
at start to INTx
↑
See Note 5
8
8
RCLK
cycles
td7
Delay time, IOW high or low (WR THR) to INTx
↑
See Note 5
16
32
RCLK
cycles
td8
Delay time, TXx
↓
at start to TXRDY
↓
CL = 100 pF
8
RCLK
cycles
tpd1
tpd2
tpd3
NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop-bit time.
Propagation delay time, IOW (WR THR)
↓
to INTx
↓
CL = 100 pF
CL = 100 pF
CL = 100 pF
35
ns
Propagation delay time, IOR (RD IIR)
↑
to INTx
↓
30
ns
Propagation delay time, IOW (WR THR)
↑
to TXRDY
↑
50
ns
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9 through 13)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td9
Delay time, stop bit to INTx
↑
or stop bit to RXRDY
↓
or read RBR to set interrupt
See Note 6
1
RCLK
cycle
tpd4
Propagation delay time, Read RBR/LSR to INTx
↓
/LSR interrupt
↓
CL = 100 pF,
See Note 7
40
ns
tpd5
NOTES:
Propagation delay time, IOR RCLK
↓
to RXRDY
↑
See Note 7
30
ns
6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are
delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status
indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after
IOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.
7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.
modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, C
L
= 100 pF (see Figures 14, 15, 16, and 17)
PARAMETER
MIN
MAX
UNIT
tpd6
tpd7
tpd8
tpd9
Propagation delay time, IOW (WR MCR)
↑
to RTSx, DTRx
↑
Propagation delay time, modem input CTSx, DSRx, and DCDx
↓↑
to INTx
↑
Propagation delay time, IOR (RD MSR)
↑
to interrupt
↓
Propagation delay time, RIx
↑
to INTx
↑
50
ns
30
ns
35
ns
30
ns
tpd10
Propagation delay time, CTS low to SOUT
↓
(See Note 7)
24
baudout
cycles
tsu6
Setup time CTS high to midpoint of Tx stop bit
2
baudout
cycles
tpd11
Propagation delay time, RCV threshold byte to RTS
↑
2
baudout
cycles
tpd12
Propagation delay time, IOR (RD RBR) low (read of last byte in receive FIFO) to RTS
↓
2
baudout
cycles
tpd13
Propagation delay time, first data bit of 16th character to RTS
↑
2
baudout
cycles
tpd14
Propagation delay time, IOR (RD RBR) low to RTS
↓
2
baudout
cycles
7. RCLK and baudout are internal signals derived from divisor latches LSB (DLL) and MSB (DLM) and input clock.
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