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參數(shù)資料
| 型號： | THS8200PFPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | GREEN, PLASTIC, HTQFP-80 |
| 文件頁數(shù)： | 63/101頁 |
| 文件大?。?/td> | 806K |
| 代理商： | THS8200PFPG4 |
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5–7
dll_bypass:
DLL bypass
{chip_ctl 0x03(6)}
[0]
0 : DLL used for clock generation; normal operation with internally generated 2
× clock. This mode should be
selected for most video formats when a 1
× clock is available on the device clock input, and either 1× or 2× DAC
operation is desired internally (as selected by register data_ifir35_bypass)
1 : DLL bypassed for clock generation. In this case the clock input on the CLKIN pin is used directly as the 2
× clock,
rather than the internally generated signal from the DLL. This mode is meant for test purposes only.
vesa_colorbars:
Color bar test pattern
{chip_ctl 0x03(5)}
[0]
0 : normal operation
1 : Device generates color bar pattern; external video inputs are ignored. The color bar pattern is only
supported in VESA PC graphics mode, with the device configured in master mode (chip_ms = 1).
dll_freq_sel:
DLL frequency range select
{chip_ctl 0x03(4)}
[0]
Sets a frequency range for the DLL 2
× clock generation. The DLL should not be used at >80 MHz. In this case the
vesa_clk register should be enabled. As a consequence, 2
× video interpolation is not available for formats with
>80 MHz pixel clock.
0 : high frequency range: pixel clock from 40–80 MHz
1 : low frequency range: pixel clock from 10–40 MHz
dac_pwdn:
DAC power down
{chip_ctl 0x03(3)}
[0]
0 : normal operation
1 : DACs go into power-down state.
chip_pwdn:
Chip power down
{chip_ctl 0x03(2)}
[0]
0 : normal operation
1 : power down of all digital logic except I2C
chip_ms:
Chip mode select
{chip_ctl 0x03(1)}
[0]
0 : slave mode. Device synchronizes to incoming video sync signals, either embedded in ITU-R.BT656 interface or
received from dedicated timing signals.
1 : master mode. Device requests video data and generates video input timing signals to external (memory) device,
according to the programmed frame/field format. Master mode is only available when the DTG is operating in VESA
mode (PC graphics signals).
arst_func_n:
Chip software reset
{chip_ctl 0x03(0)}
[1]
0 : functional block goes into reset state. I2C registers retain values.
Note: the user needs to issue a software reset after input video is disconnected from the input bus and recon-
nected (e.g. after a video format change), in order to synchronize the internal display timing generator to the
input video source properly.
1 : normal operation
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