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| 型號： | THS8200PFPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | GREEN, PLASTIC, HTQFP-80 |
| 文件頁數(shù)： | 5/101頁 |
| 文件大?。?/td> | 806K |
| 代理商： | THS8200PFPG4 |
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2–2
Table 2–1. Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
TYPE
DESCRIPTION
ABPb
15
O
Analog output of DAC2. See AGY.
ARPr
17
O
Analog output of DAC3. See AGY.
AGY
13
O
Analog output of DAC1. With the proper setting of FSADJ<n>, this output is capable of driving 1.3 V full
scale into a 37.5
load
AVDD
11, 14, 18
PWR
Analog power supply, nominal 3.3 V
AVSS
12, 16
PWR
Analog ground
BCb[9:0]
21–30
I
10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the video data source. In
30-bit mode, the B data of RGB, or the Cb data of YCbCr, should be connected to this port. In 10-bit input
mode, this port is unused. In 20-bit input mode, this port is used for CbCr input data.
CLKIN
3
I
Main clock input. Video input data on the GY[9:0]/BCb[9:0]/RCr[9:0] ports should be synchronized to
CLKIN. Depending on the input data format, CLKIN is supplied to THS8200 at 1
or 2
the pixel clock
frequency.
COMP1
10
P
Compensation pin for the internal reference amplifier. A 0.1
F capacitor should be connected between
COMP1 and analog power supply AVDD.
COMP2
9
P
Compensation pin for the internal reference amplifier. A 0.1
F capacitor should be connected between
COMP2 and analog power supply AVDD.
D1CLKO
71
O
Video ITU-R.BT656-compliant clock output. This clock output is off by default and should be activated via
an I2C register setting.
DO[9:5]
DO[4:0]
65–69
73–77
O
ITU-R.BT656 compliant video data output port. Only available when ITU-R.BT656 input format is used. Can
be used to connect to external PAL/NTSC video encoder. This port is off by default and should be activated
via an I2C register setting.
DVDD
32, 59, 79
PWR
Digital core power, nominal 1.8 V
DVSS
31, 58, 78
PWR
Digital core ground
FID
47
I
Field identification signal for interlaced video formats. In slave timing mode, this is an input from the video
data source. In master timing mode this signal is unused, as only progressive-scan VESA formats are
supported in master mode.
FSADJ1
7
P
Full scale adjustment control 1. A resistor should be connected between FSADJ1 and analog ground
AGND to control the full-scale output current of the DAC output channels. Via the data_fsadj I2C
programming register, the user can select between two full-scale ranges, determined by FSADJ1 or
FSADJ2.
For 700-mV video output (1 Vpp including sync), the nominal value is 2.99 k
; for 1.0-Vpp video output (1.3
Vpp including sync) output the nominal value is 2.08 k
.
FSADJ2
8
P
Full scale adjustment control 2. See FSADJ1.
GND_DLL
2
PWR
Ground of clock doubler. Should be connected to analog ground
GND_IO
20, 45, 72
PWR
I/O ring ground
GY[9:0]
48–57
I
10-bit video data input port. All 10 bits or the 8 MSB of this port can be connected to the video data source.
The G data of RGB or the Y data of YCbCr should be connected to this port. Port used in 10-bit mode for
CbYCrY video input data; in 20-bit input mode for Y data.
HS_IN
43
I/O
Horizontal source synchronization. In slave timing mode, this is an input from the video data source. In
master timing mode, this is an output to the video data source with programmable timing and polarity,
serving as a horizontal data qualification signal to the video source.
HS_OUT
61
O
Horizontal sync output (to display). Irrespective of slave/master timing mode configuration, this is always an
output with timing generated by the DTG.
I2CA
5
I
I2C device address LSB selection
N.C.
1, 80
I
Manufacturing test input. Must be tied to GND for normal operation.
PBKG
(VSS)
6
PWR
Substrate ground. Should be connected to analog ground
I = input, O = output, B = bidirectional, PWR = power or ground, P = passive
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