參數(shù)資料
型號(hào): THS8135-240CPHP
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48
封裝: POWER, TQFP-48
文件頁(yè)數(shù): 24/24頁(yè)
文件大?。?/td> 546K
代理商: THS8135-240CPHP
THS8135
TRIPLE 10-BIT, 80/240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO (ITU-R.BT601)
– COMPLIANT FULL SCALE RANGE
SLVSXXXX—10/02/00 3:44 PM
10
Copyright 2000 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
input code ranges for RGB resp. YCbCr operation on each of the input data busses. If codes outside this
range are supplied, they are clipped inside the DAC to the respective min/max.value for the corresponding
color component as shown in Table 8. Therefore undershoot/overshoot present in the digital domain will not
be detectable on the analog output. Note that while THS8135 allows reduced code range with RGB data,
video systems will normally use it only with YCbCr type data.
Table 8: Input code ranges for ITU.BT601 modes
Operating Mode
GY[]
RPr[]
BPb[]
RGB
64-940
YCbCr
64-940
64-960
Internally the device uses digital scaling to accommodate the full 10-bit DAC range from this reduced range.
The architecture is optimized to maintain a high linearity and avoids truncation errors in this scaling process.
If the DAC termination is such that the full-scale current corresponds e.g. to a 700mV video output in full-
scale mode (as will be the case when the DAC is terminated by 37.5 Ohm and its nominal RFS is applied) for
a 1024 input code swing, then in reduced scale mode the resulting full-scale current will also produce a
700mV analog output compliance for a 876(=940-64) code swing on the Y channel and a 896(=960-64) code
swing on the Pb and Pr channels.
Finally in all modes, the sync insertion on the analog outputs will be such that a standard-compliant sync
amplitude is generated. To guarantee this, the ratio of the DAC’s analog full-scale video output (equal in
either full or reduced scale modes, as explained above) to the sync amplitude output is fixed and nominally a
7:3 ratio (700mV video vs. 300mV for both negative positive sync excursion amplitude). This ratio is
maintained also in reduced scale ITU-R.BT601 mode. Therefore the sync amplitude will maintain its 7:3 ratio,
irrespective of either mode, and will also scale proportionally with the video amplitude if FSADJ is changed.
Backward compatibility with THS8133
Power supply
THS8135 is a functional superset to THS8133 and is footprint compatible i.e. a board designed for THS8133
can also be used with THS8135. Both devices come in the same package and have identical pinouts.
Only the power supply levels need to be adjusted, as shown in Table 9:
Table 9: Power Supply changes THS8133 vs THS8135
THS8133
THS8135
AVDD
5V
3.3V
DVDD
3.3V or 5V
1.8V
相關(guān)PDF資料
PDF描述
THS8135PHP PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8135PHPG4 PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8136IPHPQ1 PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48
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THS8136PHPR PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48
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