參數(shù)資料
型號(hào)： THS8083-95CPZP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 46/61頁(yè)
文件大?。?/td> 239K
代理商： THS8083-95CPZP
5–6
5.4.8
Output Formatter/Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
Maximum conversion rate
THS8083
80
MHz
fclk
Maximum conversion rate
THS8083-95
95
MHz
fclk
Minimum conversion rate
10
MHz
tsu(OUT)
Setup time
3
ns
th(OUT),
th(DHS)
Hold time
With respect to 50% level of rising
edge on DATACLK
1
ns
tsu(DHS)
Setup time
edge on DATACLK
4
ns
tPLH(OE)
Propagation (delay) time, low-to-high
See Note 13
8.5
ns
tPHL(OE)
Propagation (delay) time, high-to-low-level output
See Note 13
8
ns
DATACLK1 output duty cycle
40%
58%
HS and data pipeline delay
See Note 14
See timing diagrams
NOTES: 13. Output timing – OE timing tPLH(OE) is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The
digital output load is not higher than 10 pF.
OEtimingtPHL(OE)ismeasuredfromtheVIL(MAX)levelofOEtotheinstantwhentheoutputdatareachesVOH(min)orVOL(max)output
levels. The digital output load is not higher than 10 pF.
14. Pipeline delay (latency) – The number of clock cycles between conversion initiation on an input sample and the corresponding output
data being made available. Once the data pipeline is full, new valid output data are provided every clock cycle.
5.4.9
PLL
5.4.9.1 Open Loop
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DTO frequency range f
THS8083CPHP
10
80
MHz
DTO frequency range, f(DTO)
THS8083-95CPHP
10
95
MHz
Instantaneous jitter, t(INS)
260 (p-p)
ps
Short term jitter t
See Note 15
525 (p-p)
150 (rms)
ps
Short-term jitter, t(JOS)
TA = 25°C
900 (p-p)
360 (rms)
ps
Phase Increment
11.25
Monotonic
deg
NOTE 15: PLL characterization:
Instantaneous jitter is the pk-pk variation of position of clock rising edge between succeeding periods.
Short term jitter in open loop or closed loop is defined as the variation within one PLL update period (= within the same video line) of
the clock rising edge. This can be measured visually by capturing the clock and displaying it on a digital scope with a persistency of
one video line. Numerically the time instants of the rising edges, at a defined voltage level, of a number N of clock cycles (N = 800)
are captured at high sampling rate. From these time instants, the average clock time period is calculated. The deviation between
each actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value
along one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
THS8083A 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 8 BIT 80 MSPS 3.3V VIDEO AND GRAPHICS
THS8083A95 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRIPLE 8-BIT, 95MSPS, 3.3V VIDEO AND GRAPHICS
THS8083A95PZP 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8B 95MSPS 3.3V Vid & Graphics Dig RoHS:否 制造商:Texas Instruments 輸入信號(hào)類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
THS8083APZP 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Triple 8B 80 MSPS 3.3V YUV/RGB RoHS:否 制造商:Texas Instruments 輸入信號(hào)類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
THS8083APZP 制造商:Texas Instruments 功能描述:8BIT ADC 80MSPS TRIPLE SMD 8083
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