參數(shù)資料
型號: THS12082DA
廠商: Texas Instruments, Inc.
英文描述: 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
中文描述: 12位,8 MSPS的同步采樣模擬數(shù)字轉換器
文件頁數(shù): 15/38頁
文件大?。?/td> 517K
代理商: THS12082DA
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271 – MAY 2000
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
reading data from the FIFO (continued)
In Figure 8, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 8. Trigger Level 14 Selected
READ is always the logical combination of CS0, CS1 and RD.
ADC control register
The THS12082 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the
desired mode. The bit definitions of both control registers are shown in Table 7.
Table 7. Bit Definitions of Control Register CR0 and CR1
BIT
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CR0
TEST1
TEST0
SCAN
DIFF1
DIFF0
CHSEL1
CHSEL0
PD
MODE
VREF
CR1
RBACK
OFFSET
BIN/2’s
R/W
DATA_P
DATA_T
TRIG1
TRIG0
OVFL/FRST
RESET
writing to control register 0 and control register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control
register and writing the register value to the ADC. The addressing is performed with the upper data bits D10
and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0
to D9 contain the desired control register value. Table 8 shows the addressing of each control register.
Table 8. Control Register Addressing
D0 – D9
D10/RA0
D11/RA1
Addressed Control Register
Desired register value
0
0
Control register 0
Desired register value
1
0
Control register 1
Desired register value
0
1
Reserved for future
Desired register value
1
1
Reserved for future
P
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