參數(shù)資料
型號(hào): THS12082DA
廠商: Texas Instruments, Inc.
英文描述: 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
中文描述: 12位,8 MSPS的同步采樣模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 10/38頁
文件大?。?/td> 517K
代理商: THS12082DA
THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271 – MAY 2000
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
sampling rate (continued)
Table 2. Maximum Conversion Rate in Single Conversion Mode
CHANNEL CONFIGURATION
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
4 MSPS
2 single-ended channels
2
2.67 MSPS
1 differential channel
1
4 MSPS
In single conversion mode, a single conversion of the selected analog input channels is performed. The single
conversion mode is selected by setting bit 1 of control register 0 to 1.
A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and
hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence
for the selected channels is started.
The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal
DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted
sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode
can be selected according to Table 13.
Figure 1 shows the timing of the single conversion mode. In this mode, up to two analog input channels can be
selected to be sampled simultaneously (see Table 2).
CONVST
AIN
Sample N
t1
t1
td(A)
t2
tDATA_AV
DATA_AV,
Trigger Level = 1
Figure 1. Timing of Single Conversion Mode
The time (t
2
) between consecutive starts of single conversions is dependent on the number of selected analog
input channels. The time t
DATA_AV
, until DATA_AV becomes active is given by: t
DATA_AV
= t
pipe
+ n
×
t
c
. This
equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all
other trigger level conditions refer to the timing specifications of single conversion mode.
P
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