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參數(shù)資料
| 型號： | TFP503PZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大?。?/td> | 624K |
| 代理商： | TFP503PZP |
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TFP503
PanelBus HDCP DIGITAL RECEIVER
SLDS149 AUGUST 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
PGND
98
PLL ground. Ground reference and current return for internal PLL.
PIXS
4
I
Pixel select. Selects between 1- or 2-pixel/clock output mode. During 2-pixel/clock mode, both even pixels,
QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1-pixel/clock, even
and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0].
(The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel.)
High: 2-pixel/clock mode
Low: 1-pixel/clock mode
PVDD (1, 2)
97, 99
PLL VDD. Power supply for internal PLL. Nominally 3.3 V.
QE[0:7]
1017
O
Even blue pixel output. Output for even and odd blue pixels when in 1-pixel/clock mode. Output for only even
blue pixels when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE0 (terminal 10)
MSB: QE7 (terminal 17)
QE[8:15]
2027
O
Even green pixel output. Output for even and odd green pixels when in 1-pixel/clock mode. Output for only
even green pixels when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE8 (terminal 20)
MSB: QE15 (terminal 27)
QE[16:23]
3037
O
Even red pixel output. Output for even and odd red pixels when in 1-pixel/clock mode. Output for only even red
pixels when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE16 (terminal 30)
MSB: QE23 (terminal 37)
QO[0:7]
4956
O
Odd blue pixel output. Output for only odd blue pixels when in 2-pixel/clock mode. Not used and held low when
in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO0 (terminal 49)
MSB: QO7 (terminal 56)
QO[8:15]
5966
O
Odd green pixel output. Output for only odd green pixels when in 2-pixel/clock mode. Not used and held low
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO8 (terminal 59)
MSB: QO15 (terminal 66)
QO[16:23]
6975,
77
O
Odd red pixel output. Output for only odd red pixels when in 2-pixel/clock mode. Not used and held low when in
1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO16 (terminal 69)
MSB: QO23 (terminal 77)
RCL
RDA
95
96
I/O
These terminals are the I2C interface to the internal HDCP key EEPROM. Each terminal requires a 10-k
pullup resistor connected to VDD.
RSVD
42
O
Reserved. Must be tied high for normal operation.
Rx2+
80
I
Channel-2 positive receiver input. Positive side of channel-2 T.M.D.S. low-voltage signal differential input pair.
Channel-2 receives red pixel data in active display and CTL2 control signals during blanking.
Rx2
81
I
Channel-2 negative receiver input. Negative side of channel-2 T.M.D.S. low-voltage signal differential input
pair.
Rx1+
83
I
Channel-1 positive receiver input. Positive side of channel-1 T.M.D.S. low-voltage signal differential input pair.
Channel-1 receives green pixel data in active display and CTL1 control signals during blanking.
Rx1
84
I
Channel-1 negative receiver input. Negative side of channel-1 T.M.D.S. low-voltage signal differential input
pair.
Rx0+
86
I
Channel-0 positive receiver input. Positive side of channel-0 T.M.D.S. low-voltage signal differential input pair.
Channel-0 receives blue pixel data in active display and HSYNC and VSYNC control signals during blanking.
Rx0
87
I
Channel-0 negative receiver input. Negative side of channel-0 T.M.D.S. low-voltage signal differential input
pair.
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