參數(shù)資料
型號(hào)： TC9324F
廠商： Toshiba Corporation
英文描述： Single-Chip DTS Microcontroller (DTS-20)
中文描述： 單芯片微丘（丘- 20）
文件頁(yè)數(shù)： 89/101頁(yè)
文件大?。?/td> 1831K
代理商： TC9324F
TC9324F
2002-02-08
89
The pull-up/pull-down settings are useful for a key matrix structure where an I/O port output is set as
the key matrix output and (pulled-up or pulled-down) I/O port 8 is set as the input. A low-noise key
matrix can be formed by the following method. If I/O port 8 is pulled down, detect key input by setting the
key matrix output side to high impedance (input state), outputting/scanning an H level signal to the key
input line, and reading the input state of I/O port 8. If I/O port 8 is pulled up, detect key input by
outputting an L level signal to the key input line in the same way.
While the CKSTP or WAIT instruction is being executed, the key input can also be detected and the
system can be restarted. If the restart is during execution of the CKSTP instruction, I/O port 1 is pulled up.
Because all the I/O port outputs are set to L during Clock Stop mode, I/O port 8 waits in pulled-up state.
Pressing a key changes the I/O port 8 input and restarts the system. Be sure to remember that a 100-ms
standby period follows the release of Clock Stop mode at this time. Because the release of the WAIT
instruction holds the output state, the system can be restarted either by a pull-up or pull-down, and
because there is no standby after the release of the WAIT instruction, a key input can be immediately
detected or implemented. Current dissipation can be minimized by using both these backup modes
together.
As the I/O port 8 input is the inverter input, I/O port 8 input cannot be used for methods involving
intermediate potential. However, because other I/O ports input is on only when the input instruction is
executed, inputting intermediate potential will not result in abnormal current dissipation. This allows such
advantages as pull-ups with a lower potential than the V
DD
potential and the use of three-value output.
I/O ports 2 and 3 are CMOS I/O ports, also used for 8-bit A/D converter input.
I/O ports 4 and 5 are CMOS I/O ports. Pin P5-0 is also used for the buzzer output. Pins P4-1 to 3 and
P5-1 to 3 are also used as serial interface pins.
I/O ports 6 and 7 are CMOS I/O ports.
I/O ports 9 and 10 are CMOS I/O ports and are also used as the LCD driver. A reset sets these pins as I/O
port input pins.
89
88
90
85
84
87
86
91
P8-3
V
DD
P8-2
P8-1
P8-0
P7-3
P7-2
P7-1
P7-0
Example of Key Input Matrix
Circuit Structure
P7-3
P7-2
P7-1
P7-0
High impedance
P8-3
P8-2
P8-1
P8-0
Pulled up
Pulled up
Pulled up
P7-3 and P8-1 keys pressed
I/O port 8
data loading
The diagram at left is an example of the
structure of a key input matrix circuit. When no
key is pressed, the ports are pulled up. Pressing a
key inputs a source side (I/O port 9) L level signal.
Be sure to keep in mind the time for the transition
from L level to key input pull-up.
Setting all the key source-side ports to L during
WAIT instruction execution releases the WAIT
instruction whenever a key is pressed.
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