參數(shù)資料
型號(hào)： TC9324F
廠商： Toshiba Corporation
英文描述： Single-Chip DTS Microcontroller (DTS-20)
中文描述： 單芯片微丘（丘- 20）
文件頁(yè)數(shù)： 75/101頁(yè)
文件大?。?/td> 1831K
代理商： TC9324F
TC9324F
2002-02-08
75
6)
CK0, CK1 Bits
The CK0, CK1 bits select the serial clock frequency when TC9324F is selected as the master.
Because the frequency varies according to the CPU clock used, select the frequency in accordance
with your specifications. The clock duty is 50%.
Note: The output frequency varies in accordance with the operating clock of the CPU used.
When TC9324F is set as a slave, CK0 and CK1 are don’t care. When set as a slave, input a shift
clock no higher than the frequency indicated by the asterisk (
*
).
7)
SCK3/SCK4, SO3/SO4 Bits
When the ENA bit is set to 1 with the SCK3/SCK4, SO3/SO4 pins set as outputs (by the port 5 I/O
control and SCKO/SI1S bits), the SCK3/SCK4 and SO3/SO4 bit data are output as-are.
When two-line serial interface is selected, the SCK3/SCK4 and SO3/SO4 bits are set to 1 under the
following conditions.
On a shift clock (SCK4) rising edge after the SDANG_F/F bit is detected as 1 (data output
result flag NG)
On a shift clock (SCK4) rising edge after the STP F/F bit is detected as 1 (two-line serial
interface terminated)
Also, when two-line serial interface is selected, the SCK3/SCK4 bit is reset to 0 under the following
condition. (The SO3/SO4 bits are not reset by a serial operation.)
On a shift clock (SCK4) falling edge at completion of a shift operation
8)
SI3S Bit
The SI3S bit switches the serial interface data input/output. Setting SI3S to 1 selects the P5-2/SO3
pin as a serial output and the P5-1/SI3 pin as a serial input. When using the P5-1/SI3 pin as a serial
input, the P5-1 I/O control port must be set to input. Setting SI3S to 0 selects the P5-2/SO3 pin as a
serial input and the P5-1/SI3 pin as an I/O port input/output (P5-1).
The SI3S bit is used to switch the SO3 pin input/output; the input/output switching is updated
under the following conditions.
egde
SCKINV
SI3S bit updating
0
1
After STA
=
1 set, updates on serial clock (SCK3/SCK4) falling edge.
1
0
After STA
=
1 set, updates on serial clock (SCK3/SCK4) rising edge.
0
0
1
1
Updates when STA
=
1.
9)
Nch Bit
The Nch bit selects CMOS output or N-channel open drain output when the SO3/SO4 and
SCK3/SCK4 pins are set to output. Setting the Nch bit to 0 sets CMOS output; setting Nch to 1 sets
N-channel open drain output. When N-channel open drain is set, the serial clock operation wait
function and the serial data output monitor function operate (see the section on the SO-NG F/F).
The serial clock wait function pauses the serial clock output when TC9324F is set as a master
(serial clock output set) and the serial output clock is set to forcible wait by an external device (which
sets the serial clock to L).
Serial clock output frequency
4.5 MHz
CK1
CK0
75 kHz
0
0
450 kHz
*
37.5 kHz
*
0
1
150 kHz
12.5 kHz
1
0
225 kHz
17.75 kHz
1
1
75 kHz
6.25 kHz
(Note)
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