- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385912 > TC86R4600 (Toshiba Corporation) 64 Bit RISC Microprocessor(64位精簡指令集微處理器) PDF資料下載
參數(shù)資料
| 型號： | TC86R4600 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64 Bit RISC Microprocessor(64位精簡指令集微處理器) |
| 中文描述： | 64位RISC微處理器（64位精簡指令集微處理器） |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 267K |
| 代理商： | TC86R4600 |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
TC86R4600 64-bit RISC Microprocessor
T O S H IB A A M E R IC A E L E C T R O N IC C O M P O N E N T S , IN C
.
5
The Memory Management Unit controls the virtual memory
system page mapping. It consists of an instruction address trans-
lation buffer (the ITLB), a data address translation buffer (the
DTLB), a joint TLB (the JTLB), and co-processor registers used
for the virtual memory mapping sub-system.
System Control Co-Processor Registers
The R4600 incorporates all system control co-processor (CP0)
registers on-chip. These registers provide the path through which
the virtual memory systems page mapping is examined and
changed, exceptions are handled, and operating modes are con-
trolled (kernel vs. user mode, interrupts enabled or disabled,
cache features). In addition, the R4600 includes registers to
implement a real-time cycle counting facility, to aid in cache
diagnostic testing, and to assist in data error detection.
Figure 4 on page 5 shows the CP0 registers.
Virtual to Physical Address Mapping
The R4600 provides three modes of virtual
addressing:
￥ user mode
￥ supervisor mode
￥ kernel mode
This mechanism is available to system software to provide a
secure environment for user processes. Bits in a status register
determine which virtual addressing mode is used. In the user
mode, the R4600 provides a single, uniform virtual address space
of 256GB (2GB for 32-bit mode).
When operating in the kernel mode, four distinct virtual
address spaces, totalling 1024GB (4GB in 32-bit mode), are
simultaneously available and are differentiated by the high-order
bits of the virtual address.
The R4600 processors also support a supervisor mode in
which the virtual address space is 256.5GB (2.5GB in 32-bit
mode), divided into three regions based on the high-order bits of
the virtual address.
Figure 5 on page 6 shows the address space layout for 32-bit
operation.
When the R4600 is conTgured as a 64-bit microprocessor,
the virtual address space layout is an upward compatible exten-
sion of the 32-bit virtual address space layout.
J oint TLB
For fast virtual-to-physical address decoding, the R4600 uses a
large, fully associative TLB which maps 96 virtual pages to their
corresponding physical addresses. The TLB is organized as 48
pairs of even-odd entries, and maps a virtual address and address
space identiTer into the large, 64GB physical address space.
Two mechanisms are provided to assist in controlling the
amount of mapped space, and the replacement characteristics of
various memory regions. First, the page size can be conTgured,
on a per-entry basis, to map a page size of 4KB to 16MB (in mul-
tiples of 4). A CP0 register is loaded with the page size of a map-
ping, and that size is entered into the TLB when a new entry is
written. Thus, operating systems can provide special purpose
maps; for example, a typical frame buffer can be memory
mapped using only one TLB entry.
The second mechanism controls the replacement algorithm
when a TLB miss occurs. The R4600 provides a random replace-
ment algorithm to select a TLB entry to be written with a new
mapping; however, the processor provides a mechanism whereby
a system speciTc number of mappings can be locked into the
TLB, and thus avoid being randomly replaced. This facilitates the
design of real-time systems, by allowing deterministic access to
critical software.
The joint TLB also contains information to control the cache
coherency protocol for each page. SpeciTcally, each page has
attribute bits to determine whether the coherency algorithm is:
uncached, non-coherent write-back, non-coherent write-through
write-allocate, non-coherent write-through no write-allocate.
Non-coherent write-back is typically used for both code and data
on the R4600; the write-through modes support more efTcient
frame buffer accesses than the R4000 family. The coherent
modes are supported for R4000 compatibility and generate dif-
ferent transaction types on the system interface; cache coherency
is not supported however.
Instruction TLB
The R4600 also incorporates a 2-entry instruction TLB. Each
entry maps a 4KB page. The instruction TLB improves perfor-
mance by allowing instruction address translation to occur in
parallel with data address translation. When a miss occurs on an
instruction address translation, the least-recently used ITLB entry
is Tlled from the JTLB. The operation of the ITLB is invisible to
the user.
Figure 5. The R4600 CP0 Registers
0
47
TLB
(entries protected
from TLBWR)
EntryHi
10*
EntryLo0
2*
EntryLo1
3*
PageMask
5*
Wired
6*
Random
1*
Index
0*
Status
12*
Cause
13*
EPC
14*
ErrorEPC
30*
Count
9*
Compare
11*
Context
4*
XContext
20*
PRId
15*
Config
16*
TagHi
29*
TagLo
28*
ECC
26*
CacheErr
27*
BadVAddr
8*
LLAddr
17*
* Register number
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TC8830AF | The TC8830AF is a single chip CMOS LSI for voice recording/ playback using the ADM(Adaptive Delta Modulation ) |
| TC8830F | C2MOS VOICE RECORDING/REPRODUCING LSI |
| TC9020 | Gigabit Ethernet Controller |
| TC9021 | Gigabit Ethernet Controller |
| TC90A53F | 3-LINE DIGITAL Y / C SEPARATOR IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC86W-1-101 | 功能描述:TRIMMER 100 OHM 0.3W TH RoHS:是 類別:電位計(jì)，可變電阻器 >> 微調(diào)器 系列:Trimpot® TC86 - 開放框架 標(biāo)準(zhǔn)包裝:500 系列:Trimpot® TC86 - 開放框架 電阻（歐姆）:100k 功率（瓦特）:0.3W 容差:±20% 溫度系數(shù):±250ppm/°C 匝數(shù):單路 調(diào)節(jié)型:頂部調(diào)節(jié) 電阻材料:金屬陶瓷 安裝類型:通孔 端接類型:PC 引腳 包裝:散裝 尺寸/尺寸:方形 - 0.303" L x 0.268" W x 0.299" H（7.70mm x 6.80mm x 7.60mm） 其它名稱:TC86P-104 |
| TC86W-1-102 | 功能描述:TRIMMER 1K OHM 0.3W TH RoHS:是 類別:電位計(jì)，可變電阻器 >> 微調(diào)器 系列:Trimpot® TC86 - 開放框架 標(biāo)準(zhǔn)包裝:500 系列:Trimpot® TC86 - 開放框架 電阻（歐姆）:100k 功率（瓦特）:0.3W 容差:±20% 溫度系數(shù):±250ppm/°C 匝數(shù):單路 調(diào)節(jié)型:頂部調(diào)節(jié) 電阻材料:金屬陶瓷 安裝類型:通孔 端接類型:PC 引腳 包裝:散裝 尺寸/尺寸:方形 - 0.303" L x 0.268" W x 0.299" H（7.70mm x 6.80mm x 7.60mm） 其它名稱:TC86P-104 |
| TC86W-1-103 | 功能描述:TRIMMER 10K OHM 0.3W TH RoHS:是 類別:電位計(jì)，可變電阻器 >> 微調(diào)器 系列:Trimpot® TC86 - 開放框架 標(biāo)準(zhǔn)包裝:500 系列:Trimpot® TC86 - 開放框架 電阻（歐姆）:100k 功率（瓦特）:0.3W 容差:±20% 溫度系數(shù):±250ppm/°C 匝數(shù):單路 調(diào)節(jié)型:頂部調(diào)節(jié) 電阻材料:金屬陶瓷 安裝類型:通孔 端接類型:PC 引腳 包裝:散裝 尺寸/尺寸:方形 - 0.303" L x 0.268" W x 0.299" H（7.70mm x 6.80mm x 7.60mm） 其它名稱:TC86P-104 |
| TC86W-1-104 | 功能描述:TRIMMER 100K OHM 0.3W TH RoHS:是 類別:電位計(jì)，可變電阻器 >> 微調(diào)器 系列:Trimpot® TC86 - 開放框架 標(biāo)準(zhǔn)包裝:500 系列:Trimpot® TC86 - 開放框架 電阻（歐姆）:100k 功率（瓦特）:0.3W 容差:±20% 溫度系數(shù):±250ppm/°C 匝數(shù):單路 調(diào)節(jié)型:頂部調(diào)節(jié) 電阻材料:金屬陶瓷 安裝類型:通孔 端接類型:PC 引腳 包裝:散裝 尺寸/尺寸:方形 - 0.303" L x 0.268" W x 0.299" H（7.70mm x 6.80mm x 7.60mm） 其它名稱:TC86P-104 |
| TC86W-1-105 | 功能描述:TRIMMER 1M OHM 0.3W TH RoHS:是 類別:電位計(jì)，可變電阻器 >> 微調(diào)器 系列:Trimpot® TC86 - 開放框架 標(biāo)準(zhǔn)包裝:500 系列:Trimpot® TC86 - 開放框架 電阻（歐姆）:100k 功率（瓦特）:0.3W 容差:±20% 溫度系數(shù):±250ppm/°C 匝數(shù):單路 調(diào)節(jié)型:頂部調(diào)節(jié) 電阻材料:金屬陶瓷 安裝類型:通孔 端接類型:PC 引腳 包裝:散裝 尺寸/尺寸:方形 - 0.303" L x 0.268" W x 0.299" H（7.70mm x 6.80mm x 7.60mm） 其它名稱:TC86P-104 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。