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參數(shù)資料
| 型號： | TC86R4600 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64 Bit RISC Microprocessor(64位精簡指令集微處理器) |
| 中文描述： | 64位RISC微處理器（64位精簡指令集微處理器） |
| 文件頁數(shù)： | 6/30頁 |
| 文件大小： | 267K |
| 代理商： | TC86R4600 |
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TC86R4600 64-bit RISC Microprocessor
4
T O S H IB A A M E R IC A E L E C T R O N IC C O M P O N E N T S , IN C
.
The MIPS integer unit implements a load/store architecture
with single cycle ALU operations (logical, shift, add, sub) and an
autonomous multiply/divide unit. The register resources include
32 general purpose orthogonal integer registers, the HI/LO result
registers for the integer multiply/divide unit, and the program
counter. In addition, the on-chip oating-point co-processor adds
32 oating-point registers, and a oating-point control/status
register.
Register File
The R4600 has 32 general purpose registers. These registers are
used for scalar integer operations and address calculation. The
register Tle consists of two read ports and one write port, and is
fully bypassed to minimize operation latency in the pipeline.
ALU
The R4600 ALU consists of the integer adder and logic unit. The
adder performs address calculations in addition to arithmetic
operations, and the logic unit performs all logical and shift opera-
tions. Each of these units is highly optimized and can perform an
operation in a single pipeline cycle.
Integer Multiply/Divide
The R4600 uses the oating-point unit to perform integer multi-
ply and divide. The results of the operation are placed in the
and
LO
registers. The values can then be transferred to the gen-
eral purpose register Tle using the MFHI/MFLO instructions.
Table 1 below shows the number of processor internal cycles
required between an integer multiply or divide and a subsequent
MFHI or MFLO operation, in order that no interlock or stall
occurs.
HI
Floating-Point Co-Processor
The R4600 incorporates an entire oating-point co-processor on
chip, including a oating-point register Tle and execution units.
The oating-point co-processor forms a òseamlessó interface
with the integer unit, decoding and executing instructions in par-
allel with the integer unit.
Floating-Point Units
The R4600 oating-point execution unit supports single and dou-
ble precision arithmetic, as speciTed in the IEEE Standard 754.
The execution unit is broken into a separate multiply unit and a
combined add/convert/divide/square root unit. Overlap of multi-
plies and add/subtract is supported. The multiplier is partially
pipelined, allowing a new multiply to begin every 6 cycles.
As in the R3000 and R4000, the R4600 maintains fully pre-
cise oating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely
important in mission-critical environments, such as ADA, and
highly desirable for debugging in any environment.
Table 1: Integer multiply/divide cycles
32-bit
64-bit
MULT
10
12
DIV
42
74
The oating-point units operation set includes oating-
point add, subtract, multiply, divide, square root, conversion
between Txed-point and oating-point format, conversion among
oating-point formats, and oating-point compare. These opera-
tions comply with the IEEE Standard 754.
Table 2 below gives the latencies of some of the oating-
point instructions in internal processor cycles.
Floating-Point General Register File
The oating-point register Tle is made up of sixteen 64-bit regis-
ters which can also be viewed as thirty-two 32-bit registers. With
the LDC1 and SDC1 instructions the oating-point unit can take
advantage of the 64-bit wide data cache and issue a co-processor
load or store doubleword instruction in every cycle.
The oating-point control register space contains two regis-
tersDone for determining conTguration and revision information
for the co-processor and one for control and status information.
These are primarily involved with diagnostic software, exception
handling, state saving and restoring, and control of rounding
modes.
System Control Co-processor (CP0)
The system control co-processor in the MIPS architecture is
responsible for the virtual memory sub-system, the exception
control system, and the diagnostics capability of the processor. In
the MIPS architecture, the system control co-processor (and thus
the kernel software) is implementation dependent. The R4600
CP0 is essentially identical to that of the R4000PC, except that
the
WatchLo
and
WatchHi
registers are no longer present and
the Index CACHE ops use an extra address bit to select one of
the two sets (the R4000 caches are direct mapped, instead of two-
way set associative).
Table 2: Floating-Point Cycles
Operation
Single
Precision
Double
Precision
ADD
4
4
SUB
4
4
MUL
8
8
DIV
31
60
SQRT
30
59
CMP
3
3
FIX
4
4
FLOAT
6
6
ABS
1
1
MOV
1
1
NEG
1
1
LWC1, LDC1
2
2
SWC1, SDC1
1
1
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