參數(shù)資料
型號： TC7109ACLWR
元件分類： ADC
英文描述： 1-CH 12-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 27/28頁
文件大小： 598K
代理商： TC7109ACLWR
TC7109/A
DS21456B-page 8
2002 Microchip Technology Inc.
3.1.4
ZERO INTEGRATOR PHASE
The ZI phase only occurs when an input over range
condition exists. The function of the ZI phase is to elim-
inate residual charge on the integrator capacitor after an
over range measurement. Unless removed, the residual
charge will be transferred to the auto-zero capacitor and
cause an error in the succeeding conversion.
The ZI phase virtually eliminates hysteresis, or "cross-
talk" in multiplexed systems. An over range input on
one channel will not cause an error on the next channel
measured. This feature is especially useful in thermo-
couple measurements, where unused (or broken ther-
mocouple) inputs are pulled to the positive supply rail.
During ZI, the reference capacitor is charged to the ref-
erence voltage. The signal inputs are disconnected
from the buffer and integrator. The comparator output is
connected to the buffer input, causing the integrator
output to be driven rapidly to 0V (Figure 3-1). The ZI
phase only occurs following an over range and lasts for
a maximum of 1024 clock periods.
3.1.5
DIFFERENTIAL INPUT
The TC7109A has been optimized for operation with
analog common near digital ground. With +5V and -5V
power supplies, a full ±4V full scale integrator swing
maximizes the analog section's performance.
A typical CMRR of 86dB is achieved for input differen-
tial voltages anywhere within the typical Common
mode range of 1V below the positive supply, to 1.5V
above the negative supply. However, for optimum per-
formance, the IN HI and IN LO inputs should not come
within 2V of either supply rail. Since the integrator also
swings with the Common mode voltage, care must be
exercised to ensure the integrator output does not sat-
urate. A worst case condition is near a full scale nega-
tive differential input voltage with a large positive
Common mode voltage. The negative input signal
drives the integrator positive when most of its swing
has been used up by the positive Common mode volt-
age. In such cases, the integrator swing can be
reduced to less than the recommended ±4V full scale
value, with some loss of accuracy. The integrator out-
put can swing to within 0.3V of either supply without
loss of linearity.
3.1.6
DIFFERENTIAL REFERENCE
The reference voltage can be generated anywhere
within the power supply voltage of the converter. Roll-
over voltage is the main source of Common mode
error, caused by the reference capacitor losing or gain-
ing charge, due to stray capacity on its nodes. With a
large Common mode voltage, the reference capacitor
can gain charge (increase voltage) when called upon to
de-integrate
a
positive
signal
and
lose
charge
(decrease voltage) when called upon to de-integrate a
negative input signal. This difference in reference for
(+) or (–) input voltages will cause a rollover error. This
error can be held to less than 0.5 count, worst case, by
using a large reference capacitor in comparison to the
stray capacitance. To minimize rollover error from
these sources, keep the reference Common mode
voltage near or at analog common.
3.2
Digital Section
The digital section is shown in Figure 3-2 and includes
the clock oscillator and scaling circuit, a 12-bit binary
counter with output latches and TTL compatible three-
state output drivers, UART handshake logic, polarity,
over range, and control logic. Logic levels are referred
to as LOW or HIGH.
Inputs driven from TTL gates should have 3k
to 5k
pull-up resistors added for maximum noise immunity.
For minimum power consumption, all inputs should
swing from GND (LOW) to V+ (HIGH).
3.2.1
STATUS OUTPUT
During a conversion cycle, the STATUS output goes
high at the beginning of signal integrate and goes low
one-half clock period after new data from the conver-
sion has been stored in the output latches (see
Figure 3-1). The signal may be used as a "data valid"
flag to drive interrupts, or for monitoring the status of
the converter. (Data will not change while status is low.)
3.2.2
MODE INPUT
The Output mode of the converter is controlled by the
MODE input. The converter is in its "Direct" Output
mode, when the MODE input is LOW or left open. The
output data is directly accessible under the control of
the chip and byte enable inputs (this input is provided
with a pull-down resistor to ensure a LOW level when
the pin is left open). When the MODE input is pulsed
high, the converter enters the UART Handshake mode
and outputs the data in 2 bytes, then returns to "Direct"
mode. When the MODE input is kept HIGH, the con-
verter will output data in the Handshake mode at the
end of every conversion cycle. With MODE = 0 (direct
bus transfer), the send input should be tied to V+. (See
"Handshake Mode".)
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