參數(shù)資料
型號(hào): TC58DVM72A1FT00
廠商: Toshiba Corporation
英文描述: 128-MBIT (16M x 8 BITS/8M x 16BITS) CMOS NAND E2PROM
中文描述: 128兆位(16米x 8 BITS/8M x 16位)的CMOS NAND型E2PROM的
文件頁(yè)數(shù): 19/34頁(yè)
文件大小: 369K
代理商: TC58DVM72A1FT00
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
2003-01-24 19/34
DEVICE OPERATION
Read Mode (1)
Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for
timing details and the block diagram.
X8 : m=527
X16 : m=263
Read Mode (2) x8 only
Select page
N
The operation of the device after input of the 01H command is
the same as that of Read mode (1). If the start pointer is to be set
after column address 256, use Read mode (2).
BY
/
RY
WE
CLE
RE
M
N
Start-address input
Busy
01H
CE
ALE
I/O
Cell array
Select page
N
M
Figure 4. Read mode (2) operation
527
256
BY
/
RY
WE
CLE
RE
M
N
Start-address input
Busy
00H
CE
ALE
I/O
Cell array
M
Figure 3. Read mode (1) operation
m
A data transfer operation from the cell array to the register
starts on the rising edge of WE in the third cycle (after the
address information has been latched). The device will be in
Busy state during this transfer period. The CE signal must stay
Low after the third address input and during Busy state.
After the transfer period the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start pointer designated in the address input cycle.
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