參數(shù)資料
型號(hào): TC58DVM72A1FT00
廠商: Toshiba Corporation
英文描述: 128-MBIT (16M x 8 BITS/8M x 16BITS) CMOS NAND E2PROM
中文描述: 128兆位(16米x 8 BITS/8M x 16位)的CMOS NAND型E2PROM的
文件頁(yè)數(shù): 18/34頁(yè)
文件大?。?/td> 369K
代理商: TC58DVM72A1FT00
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
2003-01-24 18/34
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command
operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE,
ALE,
CE
,
WE
,
RE
and
WP
signals, as shown in Table 2.
Table 2. Logic table
CLE
ALE
CE
WE
RE
WP
*
1
Command Input
H
L
L
H
*
Address Input
L
H
L
H
*
Data Input
L
L
L
H
H
Serial Data Output
L
L
L
H
*
*
*
L
H
H
*
During Read (Busy)
*
*
H
*
*
*
During Programming (Busy)
*
*
*
*
*
H
During Erasing (Busy)
*
*
*
*
*
H
Program, Erase Inhibit
*
*
*
*
*
L
Standby
*
*
H
*
*
0 V/Vcc
H: V
IH
, L: V
IL
,
*
: V
IH
or V
IL
*
1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
Table 3. Command table (HEX)
First Cycle
Second Cycle
Acceptable while Busy
Serial Data Input
80

Read Mode (1)
00

Read Mode (2)
01

Read Mode (3)
50

Reset
FF

c
Auto Program
10

Auto Block Erase
60
D0
Status Read
70

c
ID Read
90

01 command isn’t implemented by x16.
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states
CLE
ALE
CE
WE
RE
I/O1~I/O16
Power
Output Select
L
L
L
H
L
Data output
Active
Output Deselect
L
L
L
H
H
High impedance
Active
H: V
IH
, L: V
IL
,
*
: V
IH
or V
IL
1
0
0
0
0
0
0
0
I/O8 7
6
5
4
3
2
I/O1
Serial data input: 80H
HEX data bit assignment
(Example)
0
0
0
0
0
0
0
0
I/O16 15 14 13 12 11 10 I/O9
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