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參數(shù)資料
| 型號： | TC55VEM208ASTN55 |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 中文描述： | 東芝馬鞍山數(shù)字集成電路硅柵CMOS |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 173K |
| 代理商： | TC55VEM208ASTN55 |
TC55VEM208ASTN40,55
2002-08-07 8/11
WRITE CYCLE 2 ( CONTROLLED)
(See Note 4)
Note:
(1)
R/W remains HIGH for the read cycle.
(2)
If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance.
(3)
If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance.
(4)
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
(5)
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
R/W
t
WC
t
AS
t
WR
t
WP
CE
t
CW
VALID DATA IN
t
ODW
t
DS
t
DH
t
COE
Hi-Z
Hi-Z
(See Note 5)
(See Note 5)
Address
A0~A18
D
OUT
I/O1~8
D
IN
I/O1~8
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