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參數(shù)資料
| 型號(hào)： | TC55VEM208ASTN55 |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
| 中文描述： | 東芝馬鞍山數(shù)字集成電路硅柵CMOS |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大小： | 173K |
| 代理商： | TC55VEM208ASTN55 |
TC55VEM208ASTN40,55
2002-08-07 3/11
DC RECOMMENDED OPERATING CONDITIONS (
Ta
=
40° to 85°C
)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
V
DD
Power Supply Voltage
2.3
3.6
V
V
DD
=
2.3 V~2.7 V
2.0
V
IH
Input High Voltage
V
DD
=
2.7 V~3.6 V
2.2
V
DD
+
0.3
V
V
IL
Input Low Voltage
0.3
*
V
DD
×
0.24
V
V
DH
Data Retention Supply Voltage
1.5
3.6
V
*
:
2.0 V when measured at a pulse width of 20ns
DC CHARACTERISTICS
(Ta
=
40° to 85°C, V
DD
=
2.3 to 3.6 V)
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP MAX UNIT
I
IL
Input Leakage
Current
Output High Current V
OH
=
V
DD
0.5 V
Output Low Current V
OL
=
0.4 V
Output Leakage
Current
V
IN
=
0 V~V
DD
±
1.0
μ
A
I
OH
I
OL
0.5
2.1
mA
mA
I
LO
CE
=
V
IH
or R/W
=
V
IL
or
OE
=
V
IH
, V
OUT
=
0 V~V
DD
±
1.0
μ
A
MIN
35
I
DDO1
CE
=
V
IL
and R/W
=
V
IH
,
I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
1
μ
s
8
mA
MIN
30
I
DDO2
Operating Current
CE
=
0.2 V and R/W
=
V
DD
0.2 V,
I
OUT
=
0 mA,
Other Input
=
V
DD
0.2 V/0.2 V
t
cycle
1
μ
s
3
mA
I
DDS1
CE
=
V
IH
1
mA
V
DD
=
3.3V
±
0.3 V Ta
=
40~85°C
10
Ta
=
25°C
0.7
Ta
=
40~40°C
2
I
DDS2
Standby Current
CE
=
V
DD
0.2 V
V
DD
=
3.0 V
Ta
=
40~85°C
5
μ
A
CAPACITANCE
(Ta
=
25°C, f
=
1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
MAX
UNIT
C
IN
Input Capacitance
V
IN
=
GND
10
pF
C
OUT
Output Capacitance
V
OUT
=
GND
10
pF
Note: This parameter is periodically sampled and is not 100% tested.
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