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| 型號： | TC510CPF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 7/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANALOG FRONT END 17BIT 24DIP |
| 標(biāo)準(zhǔn)包裝： | 17 |
| 位數(shù)： | 17 |
| 通道數(shù)： | 1 |
| 功率（瓦特）： | 18mW |
| 電壓 - 電源，模擬： | 5V |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-DIP |
| 包裝： | 管件 |
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2008 Microchip Technology Inc.
DS21428E-page 15
TC500/A/510/514
7.0
TYPICAL APPLICATIONS
7.1
Component Value Selection
The procedure outlined below allows the user to arrive
at values for the following TC5XX design variables:
1.
Integration Phase Timing.
2.
Integrator Timing Components (RINT, CINT).
3.
Auto-zero and Reference Capacitors.
4.
Voltage Reference.
7.2
Select Integration Time
Integration time must be picked as a multiple of the
period of the line frequency. For example, TINT times of
33 ms, 66 ms and 132 ms maximize 60 Hz line
rejection.
7.3
DINT and IZ Phase Timing
The duration of the DINT phase is a function of the
amount of voltage stored on the integrator during TINT
and the value of VREF. The DINT phase must be initiated
immediately following INT and terminated when an
integrator output zero-crossing is detected. In general,
the maximum number of counts chosen for DINT is twice
that of INT (with VREF chosen at VIN(MAX) /2).
7.4
Calculate Integrating Resistor
(RINT)
The desired full-scale input voltage and amplifier output
current capability determine the value of RINT. The
buffer and integrator amplifiers each have a full-scale
current of 20 μA.
The value of RINT is, therefore, directly calculated in the
following equation:
EQUATION 7-1:
7.5
Select Reference (CREF) and Auto-
zero (CAZ) Capacitors
CREF and CAZ must be low leakage capacitors (such as
polypropylene). The slower the conversion rate, the
larger the value CREF must be. Recommended
Larger values for CAZ and CREF may also be used to
limit rollover errors.
TABLE 7-1:
CREF AND CAZ SELECTION
7.6
Calculate Integrating Capacitor
(CINT)
The integrating capacitor must be selected to maximize
integrator output voltage swing. The integrator output
voltage swing is defined as the absolute value of VDD
(or VSS) less 0.9V (i.e., IVDD - 0.9VI or IVSS + 0.9VI).
Using the 20 μA buffer maximum output current, the
value of the integrating capacitor is calculated using the
following equation.
EQUATION 7-2:
It is critical that the integrating capacitor has a very low
dielectric absorption. Polypropylene capacitors are an
example of one such dialectic. Polyester and poly-
bicarbonate capacitors may also be used in less critical
applications. Table 7-2 summarizes recommended
capacitors for CINT.
TABLE 7-2:
RECOMMENDED CAPACITOR
FOR CINT
7.7
Calculate VREF
The reference de-integration voltage is calculated
using the following equation:
EQUATION 7-3:
Where:
VIN(MAX)
=
Maximum input voltage (full count
voltage)
RINT
=
Integrating Resistor (in M)
For loop stability, R
INT should be ≥ 50 k
R
INT in MΩ
()
V
IN MAX
()
20
-----------------------
=
Conversions
Per Second
Typical Value of
CREF, CAZ (μF)
Suggested* Part
Number
>7
0.1
SMR5 104K50J01L4
2 to 7
0.22
SMR5 224K50J02L4
2 or less
0.47
SMR5 474K50J04L4
* Manufactured by Evox Rifa, Inc.
Value
Suggested
Part Number*
0.1
SMR5 104K50J01L4
0.22
SMR5 224K50J02L4
0.33
SMR5 334K50J03L4
0.47
SMR5 474K50J04L4
* Manufactured by Evox Rifa, Inc.
Where:
TINT
=
Integration Period
VS
=IVDDI or IVSSI, whichever is less
(TC500/A)
VS
=IVDDI (TC510, TC514)
C
INT
T
INT
() 20 10
6
–
×
()
V
S
0.9
–
()
---------------------------------------------
=
V
REF
V
S
0.9
–
() C
INT
() R
INT
()
2T
INT
()
-----------------------------------------------------------V
=
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