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| 型號(hào)： | TC510CPF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 3/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANALOG FRONT END 17BIT 24DIP |
| 標(biāo)準(zhǔn)包裝： | 17 |
| 位數(shù)： | 17 |
| 通道數(shù)： | 1 |
| 功率（瓦特）： | 18mW |
| 電壓 - 電源，模擬： | 5V |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-DIP |
| 包裝： | 管件 |
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2008 Microchip Technology Inc.
DS21428E-page 11
TC500/A/510/514
5.0
TC500/A/510/514 CONVERTER
OPERATION
The TC500/A/510/514 incorporates an auto-zero and
Integrator phase in addition to the input signal Integrate
and reference De-integrate phases. The addition of
these phases reduce system errors, calibration steps
and shorten overrange recovery time. A typical
measurement cycle uses all four phases in the
following order:
1.
Auto-zero.
2.
Input signal integration.
3.
Reference de-integration.
4.
Integrator output zero.
The internal analog switch status for each of these
phases is summarized in Table 5-1. This table
references the Typical Application.
TABLE 5-1:
INTERNAL ANALOG GATE STATUS
5.1
Auto-zero Phase (AZ)
During this phase, errors due to buffer, integrator and
comparator offset voltages are nulled out by charging
CAZ (auto-zero capacitor) with a compensating error
voltage.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to analog common. The
reference capacitor is charged to the reference voltage
potential through SWR. A feedback loop, closed around
the integrator and comparator, charges the capacitor
(CAZ) with a voltage to compensate for buffer amplifier,
integrator and comparator offset voltages.
5.2
Analog Input Signal Integration
Phase (INT)
The TC5XX integrates the differential voltage between
the VIN+ and VIN– inputs. The differential voltage must
be within the device’s Common mode range VCMR. The
input signal polarity is normally checked via software at
the end of this phase: CMPTR = 1 for positive polarity;
CMPTR = 0 for negative polarity.
5.3
Reference Voltage De-integration
Phase (DINT)
The previously charged reference capacitor is
connected with the proper polarity to ramp the
integrator output back to zero. An externally-provided,
precision timer is used to measure the duration of this
phase. The resulting time measurement is proportional
to the magnitude of the applied input voltage.
5.4
Integrator Output Zero Phase (IZ)
This phase ensures the integrator output is at 0V when
the auto-zero phase is entered, and that only system
offset voltages are compensated. This phase is used at
the end of the reference voltage de-integration phase
and MUST be used for ALL TC5XX applications having
resolutions of 12-bits or more. If this phase is not used,
the value of the auto-zero capacitor (CAZ) must be
about 2 to 3 times the value of the integration capacitor
(CINT) to reduce the effects of charge sharing. The
integrator output zero phase should be programmed to
operate until the output of the comparator returns high.
The overall timing system is shown in Figure 5-1.
Conversion Phase
SWI
SWR+SWR-SWZ
SWR
SW1
SWIZ
Auto-zero (A = 0, B = 1)
—
Closed
—
Input Signal Integration (A = 1, B = 0)
Closed
—
Reference Voltage De-integration
(A =1, B = 1)
—
*
Closed
—
Closed
—
Integrator Output Zero (A = 0, B = 0)
—
Closed
* Assumes a positive polarity input signal. SW–RI would be closed for a negative input signal.
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