參數資料
型號: TC1268
廠商: Microchip Technology Inc.
英文描述: 500mA Fixed Output, Fast Response CMOS LDO with Shutdown
中文描述: 500mA的固定輸出,快速響應的CMOS LDO穩(wěn)壓器,帶有關斷
文件頁數: 5/12頁
文件大?。?/td> 448K
代理商: TC1268
2002 Microchip Technology Inc.
DS21379B-page 5
TC1268
3.2
Bypass Input
A 10nF capacitor connected from the bypass input to
ground
reduces
noise
present
reference, which in turn, significantly reduces output
noise. If output noise is not a concern, this input may be
left unconnected. Larger capacitor values may be
used, but this results in a longer time period to achieve
the rated output voltage, once power is initially applied.
on
the
internal
3.3
Output Capacitor
A 1
μ
F (min) capacitor from V
OUT
to ground is required.
The output capacitor should have an effective series
resistance greater than 0.1
and less than 5
, and a
resonant frequency above 1MHz. A 1
μ
F capacitor
should be connected from V
IN
to GND if there is more
than 10 inches of wire between the regulator and the
AC filter capacitor, or if a battery is used as the power
source. Aluminum electrolytic or tantalum capacitor
types can be used. (Since many aluminum electrolytic
capacitors
freeze
at
approximately
tantalums are recommended for applications operating
below -25°C.) When operating from sources other than
batteries,
supply
noise
response can be improved by increasing the value of
the input and output capacitors and employing passive
filtering techniques.
-30°C,
solid
rejection
and
transient
3.4
ERROR Output
ERROR is driven low whenever V
OUT
falls out of
regulation by more than -5% (typical). This condition
may be caused by low input voltage, output current
limiting, or thermal limiting.
The ERROR threshold is 5% below rated V
OUT
,
regardless of the programmed output voltage value
(e.g., ERROR = V
OL
at 2.375V (typ.) for a 2.5V
regulator). ERROR output operation is shown in
Figure 3-3. Note that ERROR is active when V
OUT
is at
or below V
TH
, and inactive when V
OUT
is above V
TH
+
V
H
.
As shown in Figure 3-1, ERROR can be used as a
battery low flag, or as a processor RESET signal (with
the addition of timing capacitor C1). R1 x C1 should be
chosen to maintain ERROR below V
IH
of the processor
RESET input for at least 200msec to allow time for the
system to stabilize. Pull-up resistor R1 can be tied to
V
OUT
, V
IN
or any other voltage less than (V
IN
+ 0.3V).
FIGURE 3-3:
ERROR OUTPUT
OPERATION
V
OUT
V
TH
V
IH
Hysteresis (V
H
)
V
OL
ERROR
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