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參數(shù)資料
| 型號： | TC1174VUA |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 300mA CMOS LDO with Shutdown and VREF Bypass |
| 中文描述： | 300mA的CMOS LDO穩(wěn)壓器具有關(guān)斷和VREF繞道 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 444K |
| 代理商： | TC1174VUA |
2002 Microchip Technology Inc.
DS21363B-page 5
TC1174
4.0
THERMAL CONSIDERATIONS
4.1
Thermal Shutdown
Integrated
regulator off when die temperature exceeds 150°C.
The regulator remains off until the die temperature
drops to approximately 140°C.
thermal
protection
circuitry
shuts
the
4.2
Power Dissipation
The amount of power the regulator dissipates is
primarily a function of input and output voltage, and
output current. The following equation is used to
calculate worst case actual power dissipation:
EQUATION 4-1:
The maximum allowable power dissipation (Equation
4-2) is a function of the maximum ambient temperature
(T
A
MAX
), the maximum allowable die temperature
(T
J
MAX
) and the thermal resistance from junction-to-air
(
θ
JA
). The 8-Pin SOIC package has a
θ
JA
of approxi-
mately 160°C/Watt, while the 8-Pin MSOP package
has a
θ
JA
of approximately 200°C/Watt.
EQUATION 4-2:
Equation 4-1 can be used in conjunction with Equation
4-2 to ensure regulator thermal operation is within
limits. For example:
Given:
V
IN
MAX
V
OUT
MIN
I
LOAD
MAX
= 250mA
T
J
MAX
T
A
MAX
8-Pin MSOP Package
= 3.0V + 10%
= 2.7V – 0.5%
= 125°C
= 55°C
Find: 1. Actual power dissipation
2. Maximum allowable dissipation
Actual power dissipation:
P
D
≈
(V
IN
MAX
– V
OUT
MIN
)I
LOAD
MAX
= [(3.0 x 1.1) – (2.7 x .995)]250 x 10
–3
= 155mW
Maximum allowable power dissipation:
In this example, the TC1174 dissipates a maximum of
155mW; below the allowable limit of 350mW. In a
similar manner, Equation 4-1 and Equation 4-2 can be
used to calculate maximum current and/or input
voltage limits. For example, the maximum allowable
V
IN
is found by substituting the maximum allowable
power dissipation of 350mW into Equation 4-1, from
which V
IN
MAX
= 4.1V.
4.3
Layout Considerations
The primary path of heat conduction out of the package
is via the package leads. Therefore, layouts having a
ground plane, wide traces at the pads, and wide power
supply bus lines combine to lower
θ
JA
and therefore
increase the maximum allowable power dissipation
limit.
Where:
P
D
≈
(V
IN
MAX
– V
OUT
MIN
)I
LOAD
MAX
P
D
V
IN
MAX
V
OUT
MIN
I
LOAD
MAX
= Worst case actual power dissipation
= Maximum voltage on V
IN
= Minimum regulator output voltage
= Maximum output (load) current
P
D
MAX
= (T
J
MAX
– T
A
MAX
)
θ
JA
Where all terms are previously defined.
P
D
MAX
= (T
J
MAX
– T
A
MAX
)
θ
JA
= (125 – 55)
200
= 350mW
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