參數(shù)資料
型號： TC1130
廠商： INFINEON TECHNOLOGIES AG
英文描述： 32-Bit Single-Chip Microcontroller
中文描述： 32位單片機(jī)
文件頁數(shù)： 62/113頁
文件大?。?/td> 1505K
代理商： TC1130
TC1130
Data Sheet
58
V0.3, 2003-09
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failure. The WDT helps to abort an accidental
malfunction of the TC1130 in a user-specified time period. When enabled, the WDT will
cause the TC1130 system to be reset if the WDT is not serviced within a user-
programmable time period. The CPU must service the WDT within this time interval to
prevent the WDT from causing a TC1130 system reset. Hence, routine service of the
WDT confirms that the system is functioning properly.
In addition to this standard “Watchdog” function, the WDT incorporates the EndInit
feature and monitors its modifications. A system-wide line is connected to the ENDINIT
bit implemented in a WDT control register, serving as an additional write-protection for
critical registers (besides Supervisor Mode protection). Registers protected via this line
can only be modified when Supervisor Mode is active and bit ENDINIT = 0.
A further enhancement in the TC1130’s Watchdog Timer is its reset prewarning
operation. Instead of immediately resetting the device on the detection of an error, as
known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI)
to the CPU before finally resetting the device at a specified time period later. This gives
the CPU a chance to save system state to memory for later examination of the cause of
the malfunction, an important aid in debugging.
Features
16-bit Watchdog counter
Selectable input frequency:
f
SYS
/256 or
f
SYS
/16384
16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
Incorporation of the ENDINIT bit and monitoring of its modifications
Sophisticated password access mechanism with fixed and user-definable password
fields
Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT and limited.
Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation.
Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
Double Reset Detection: If a Watchdog induced reset occurs twice without a proper
access to its control register in between, a severe system malfunction is assumed and
the TC1130 is held in reset until a power-on reset. This prevents the device from being
periodically reset if, for instance, connection to the external memory has been lost
such that even system initialization could not be performed.
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