參數(shù)資料
型號: TB31356AFL
廠商: Toshiba Corporation
英文描述: 1.8GHz,600MHz DUAL-PLL FREQUENCY SYNTHESIZER
中文描述: 配備1.8GHz,600MHz的雙鎖相環(huán)頻率合成器
文件頁數(shù): 5/10頁
文件大?。?/td> 297K
代理商: TB31356AFL
TENTATIVE TB31356AFL
(5) PLL1 divider data
This specification is design target. It is subject to change without notice
.
Nov. 27 2002 PAGE 5
l
Consist of a 6-bit swallow counter (programmable counter), a 12-bit programmable counter, and
a 1/64, 1/65 two modulus prescaler.
l
By sending any data to the swallow counter and programmable counter, number of division can
be set from 4032 to 262143.
LSB
A0 A1 A2 A3 A4 A5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 SB1 SB2 SBX 0 0 0
Swallow counter : A Programmable counter : N Battery saving
Group code
Number of divisions = 64N+A (4032 =< Number of divisions =< 262143)
A=A0+A1*2
1
.......+A5*2
5
A : Value of A counter
N=D0+D1*2
1
+.......+D11*2
11
N : Value of N counter
(6) PLL2 divider data
l
Consist of a 4-bit swallow counter (programmable counter), a 11-bit programmable counter, and
a 1/16, 1/17 two modulus prescaler.
By sending any data to the swallow counter and programmable counter, number of division can
be set from 240 to 32767.
LSB
A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 LA SB1 SB2 SBX 0 1 0
Swallow counter : A Programmable counter : N Battery saving
Group code
Number of divisions = 16N+A (240 =< Number of divisions =< 32767)
A=A0+A1*2
1
.......+A3*2
3
A : Value of A counter
N=D0+D1*2
1
+.......+D10*2
10
N : Value of N counter
l
(7) PLL1 reference divider data
l
Consist of a 12-bit reference counter (programmable counter).
l
By sending any data to the reference counter, number of division can be set from 4 to 4095
LSB
D0
D1
D2
D3
D4
D5
D6
D7
Reference counter Battery saving Group code
D8
D9 D10 D11 SB1 SB2 SBX
0
0
1
D=D0+D1*2
1
+.........D11*2
11
4 =< Number of divisions =< 4095
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